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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SMEInstrInfo.td359 defm FMLA_VG2_M2ZZI_S : sme2_multi_vec_array_vg2_index_32b<"fmla", 0b01, 0b0000, ZZ_s_mul_r, ZPR4b3…
366 defm FMLS_VG2_M2ZZI_S : sme2_multi_vec_array_vg2_index_32b<"fmls", 0b01, 0b0010, ZZ_s_mul_r, ZPR4b3…
395 defm FMLSL_MZZI : sme2_mla_long_array_index<"fmlsl", 0b10, 0b01, nxv8f16, int_aarch64_sme_f…
396 defm FMLSL_VG2_M2ZZI : sme2_fp_mla_long_array_vg2_index<"fmlsl", 0b01, nxv8f16, int_aarch64_sme_f…
397 defm FMLSL_VG4_M4ZZI : sme2_fp_mla_long_array_vg4_index<"fmlsl", 0b01, nxv8f16, int_aarch64_sme_f…
398 defm FMLSL_MZZ : sme2_mla_long_array_single<"fmlsl", 0b00, 0b01, nxv8f16, int_aarch64_sme_f…
425 defm SMLAL_MZZ : sme2_mla_long_array_single<"smlal",0b01, 0b00, nxv8i16, int_aarch64_sme_s…
431 defm SMLSL_MZZI : sme2_mla_long_array_index<"smlsl", 0b11, 0b01, nxv8i16, int_aarch64_sme_s…
432 defm SMLSL_VG2_M2ZZI : sme2_int_mla_long_array_vg2_index<"smlsl", 0b01, int_aarch64_sme_smlsl_lane…
433 defm SMLSL_VG4_M4ZZI : sme2_int_mla_long_array_vg4_index<"smlsl", 0b01, int_aarch64_sme_smlsl_lane…
[all …]
H A DAArch64SVEInstrInfo.td626 defm ORR_ZZZ : sve_int_bin_cons_log<0b01, "orr", or>;
680 defm EOR_ZI : sve_int_log_imm<0b01, "eor", "eon", xor>;
686 defm UMAX_ZI : sve_int_arith_imm1_unsigned<0b01, "umax", AArch64umax_p>;
861 defm FMLS_ZPmZZ : sve_fp_3op_p_zds_a<0b01, "fmls", "FMLS_ZPZZZ", AArch64fmls_m1, "FMSB_ZPmZZ">;
866 …defm FMSB_ZPmZZ : sve_fp_3op_p_zds_b<0b01, "fmsb", int_aarch64_sve_fmsb, "FMLS_ZPmZZ", /*isRever…
882 defm FMLS_ZZZI : sve_fp_fma_by_indexed_elem<0b01, "fmls", AArch64fmlsidx>;
1035 defm SUNPKHI_ZZ : sve_int_perm_unpk<0b01, "sunpkhi", AArch64sunpkhi>;
1059 defm BRKPB_PPzPP : sve_int_brkp<0b01, "brkpb", int_aarch64_sve_brkpb_z>;
1131 defm LD1RB_H_IMM : sve_mem_ld_dup<0b00, 0b01, "ld1rb", Z_h, ZPR16, uimm6s1>;
1134 defm LD1RSW_IMM : sve_mem_ld_dup<0b01, 0b00, "ld1rsw", Z_d, ZPR64, uimm6s4>;
[all …]
H A DSVEInstrFormats.td451 def _H : sve_int_ptrue<0b01, opc, asm, PPR16, nxv8i1, op>;
920 def _B : sve_int_pfirst_next<0b01, opc, asm, PPR8>;
927 def _H : sve_int_pfirst_next<0b01, opc, asm, PPR16>;
969 def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64as32>;
997 def _H : sve_int_count_r<0b01, opc, asm, GPR32z, PPR16, GPR32z>;
1015 def _H : sve_int_count_r<0b01, opc, asm, GPR64z, PPR16, GPR64z>;
1110 def _H : sve_int_count_v<0b01, opc, asm, ZPR16, PPR16>;
1151 def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>;
1163 def _H : sve_int_pcount_pred<0b01, opc, asm, PPR16>;
1406 def _H : sve_int_perm_dup_r<0b01, asm, ZPR16, nxv8i16, GPR32sp, op>;
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H A DAArch64InstrInfo.td1583 let Inst{20-19} = 0b01;
1599 let Inst{20-19} = 0b01;
1754 def SHA512H2 : CryptoRRRTied<0b0, 0b01, "sha512h2">;
1759 def BCAX : CryptoRRRR_16B<0b01, "bcax">;
1824 def SM3TT1B : CryptoRRRi2Tied<0b0, 0b01, "sm3tt1b">;
1829 def SM3PARTW2 : CryptoRRRTied_4S<0b1, 0b01, "sm3partw2">;
1831 def SM4E : CryptoRRTied_4S<0b0, 0b01, "sm4e">;
1863 def LDAPRH : RCPCLoad<0b01, "ldaprh", GPR32>;
2030 def IB : SignAuthOneData<prefix, 0b01, !strconcat(asm, "ib"), op>;
2035 def IZB : SignAuthZero<prefix_z, 0b01, !strconcat(asm, "izb"), op>;
[all …]
H A DAArch64InstrFormats.td2063 let Inst{20-19} = 0b01;
2078 let Inst{20-19} = 0b01;
3743 let Inst{25-24} = 0b01;
4598 let Inst{11-10} = 0b01;
5125 : BaseMemTag<0b01, 0b00, asm_insn, asm_opnds, "$Rt = $wback",
5159 BaseMemTagStore<opc1, 0b01, insn, "\t$Rt, [$Rn], $offset",
5274 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
5280 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
5288 def SDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, FPR32, asm,
5351 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
[all …]
H A DSMEInstrFormats.td403 …def NAME : sme_fp_outer_product_inst<0, 0b01, 0b00, TileOp32, ZPR8, mnemonic>, SMEPseudo2Instr<NAM…
429 …def NAME : sme_fp_outer_product_inst<0, {0, 0b1}, 0b01, TileOp16, ZPR8, mnemonic>, SMEPseudo2Instr…
900 def _H : sme_mem_ld_ss_inst<0b0, 0b01, mnemonic # "h",
1038 def _H : sme_mem_st_ss_inst<0b0, 0b01, mnemonic # "h",
1234 def _H : sme_vector_to_tile_inst<0b0, 0b01, !if(is_col, TileVectorOpV16,
1420 def _H : sme_tile_to_vector_inst<0b0, 0b01, ZPR16, !if(is_col, TileVectorOpV16,
1636 def _H : sve2_clamp<asm, 0b01, U, ZPR16>;
1658 let Inst{15-14} = 0b01;
1980 def _H : sme2_sve_destructive_vector_vg2_single<0b01, op, ZZ_h_mul_r, ZPR4b16, mnemonic>;
1987 def _H : sme2_sve_destructive_vector_vg2_single<0b01, op, ZZ_h_mul_r, ZPR4b16, mnemonic>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats16Instr.td45 let Inst{15, 14} = 0b01;
58 let Inst{15, 14} = 0b01;
71 let Inst{15, 14} = 0b01;
84 let Inst{15, 14} = 0b01;
96 let Inst{15, 14} = 0b01;
109 let Inst{15, 14} = 0b01;
120 let Inst{15, 14} = 0b01;
178 let Inst{15, 14} = 0b01;
216 let Inst{15, 14} = 0b01;
H A DCSKYInstrInfo16Instr.td65 def ADDC16 : R16_XZ_BINOP_C<0b1000, 0b01, "addc16">;
73 def XOR16 : R16_XZ_BINOP<0b1011, 0b01, "xor16", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
80 def ANDN16 : R16_XZ_BINOP<0b1010, 0b01, "andn16", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
82 def LSR16 : R16_XZ_BINOP<0b1100, 0b01, "lsr16", BinOpFrag<(srl node:$LHS, node:$RHS)>>;
86 def MULSH16 : R16_XZ_BINOP_NOPat<0b1111, 0b01, "mulsh16">;
89 def ZEXTH16 : R16_XZ_UNOP<0b1101, 0b01, "zexth16">;
182 let Inst{15,14} = 0b01;
193 let Inst{15,14} = 0b01;
221 def JSR16 : R16_X_J<0b11101111, 0b01, "jsr16"> {
293 let Inst{15, 14} = 0b01;
[all …]
H A DCSKYInstrFormatsF2.td73 def _RZ : F2_XZ_P<datatype, {sop, 0b01}, op#".rz", [], outs, ins>;
137 : F2_LDST<0b01, sop, op#".64", outs, ins>;
157 : F2_LDSTM<0b01, sop, sop2, op#".64", outs, ins>;
181 : F2_LDSTR<0b01, sop, op#".64", outs, ins>;
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsMSAInstrInfo.td338 class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
343 class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
348 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
353 class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
358 class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
363 class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
372 class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
377 class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
382 class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
387 class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoC.td261 : RVInst16CB<funct3, 0b01, (outs), (ins GPRC:$rs1, bare_simm9_lsb0:$imm),
274 : RVInst16CB<0b100, 0b01, (outs GPRC:$rd),
285 : RVInst16CA<funct6, funct2, 0b01, (outs GPRC:$rd_wb),
397 def C_NOP : RVInst16CI<0b000, 0b01, (outs), (ins), "c.nop", "">,
404 def C_ADDI : RVInst16CI<0b000, 0b01, (outs GPRNoX0:$rd_wb),
420 def C_JAL : RVInst16CJ<0b001, 0b01, (outs), (ins bare_simm12_lsb0:$offset),
425 def C_ADDIW : RVInst16CI<0b001, 0b01, (outs GPRNoX0:$rd_wb),
433 def C_LI : RVInst16CI<0b010, 0b01, (outs GPRNoX0:$rd), (ins simm6:$imm),
438 def C_ADDI16SP : RVInst16CI<0b011, 0b01, (outs SP:$rd_wb),
452 def C_LUI : RVInst16CI<0b011, 0b01, (outs GPRNoX0X2:$rd),
[all …]
H A DRISCVInstrInfoP.td86 let Inst{26-25} = 0b01;
160 def PSEXT_W_B : RVPUnaryWUF<0b01, 0b00100, "psext.w.b">;
161 def PSEXT_W_H : RVPUnaryWUF<0b01, 0b00101, "psext.w.h">;
H A DRISCVInstrInfoZcmop.td16 : RVInst16CI<0b011, 0b01, (outs), (ins), opcodestr, ""> {
H A DRISCVInstrInfoXqci.td499 : RVInstR4<0b01, funct3, OPC_CUSTOM_2, (outs GPRNoX0:$rd_wb),
584 : RVInst16CB<0b100, 0b01, (outs GPRC:$rd),
685 : RVInst16CB<0b100, 0b01, (outs), (ins uimm5slist:$slist), OpcodeStr, "$slist"> {
861 def QC_INSB : QCIBitManipRII<0b001, 0b01, GPR, "qc.insb">;
872 def QC_EXT : QCIBitManipRII<0b010, 0b01, GPRNoX0, "qc.ext">;
885 def QC_C_BSETI : QCI_RVInst16CB_BM<0b01, "qc.c.bseti">;
923 let Inst{31-30} = 0b01;
943 def QC_SWMI : QCIStoreMultiple<0b01, GPRNoX0, uimm5nonzero, "qc.swmi">;
948 def QC_LWMI : QCILoadMultiple<0b01, uimm5nonzero, "qc.lwmi">;
952 def QC_LIEQ : QCILICC<0b000, 0b01, GPRNoX0, "qc.lieq">;
[all …]
H A DRISCVInstrInfoXMips.td69 let Inst{21-20} = 0b01;
108 let Inst{8-7} = 0b01;
H A DRISCVInstrInfoXCV.td345 def CV_EXTRACTU : CVBitManipRII<0b01, 0b000, "cv.extractu">;
348 def CV_BSET : CVBitManipRII<0b01, 0b001, "cv.bset">;
384 def CV_MACHHSN : CVInstMacN<0b01, 0b110, "cv.machhsn">,
394 def CV_MACHHUN : CVInstMacN<0b01, 0b111, "cv.machhun">,
404 def CV_MULHHSN : CVInstMulN<0b01, 0b100, "cv.mulhhsn">,
414 def CV_MULHHUN : CVInstMulN<0b01, 0b101, "cv.mulhhun">,
458 def CV_ADDUN : CVInstAluRRI<0b01, 0b010, "cv.addun">,
466 def CV_SUBUN : CVInstAluRRI<0b01, 0b011, "cv.subun">,
H A DRISCVInstrFormatsV.td29 def MOPLDIndexedUnord : RISCVMOP<0b01>;
34 def MOPSTIndexedUnord : RISCVMOP<0b01>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td3336 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3350 def v4f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3363 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3377 def v8f16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3420 def v4i16 : N3VD_cmp<op24, op23, 0b01, op11_8, op4, itinD16,
3431 def v8i16 : N3VQ_cmp<op24, op23, 0b01, op11_8, op4, itinQ16,
3449 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3457 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3473 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3490 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
[all …]
H A DARMInstrVFP.td167 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
172 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
182 def VLDRH : AHI5<0b1101, 0b01, (outs HPR:$Sd), (ins addrmode5fp16:$addr),
247 let Inst{24-23} = 0b01; // Increment After
256 let Inst{24-23} = 0b01; // Increment After
275 let Inst{24-23} = 0b01; // Increment After
288 let Inst{24-23} = 0b01; // Increment After
404 let Inst{24-23} = 0b01; // Increment After
411 let Inst{24-23} = 0b01; // Increment After
588 defm VSELVS : vsel_inst<"vs", 0b01, 6>;
[all …]
H A DARMInstrMVE.td290 def MVE_v8i16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "i", ?>;
298 def MVE_v8s16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "s", 0b0>;
302 def MVE_v8u16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "u", 0b1>;
307 def MVE_v8f16 : MVEVectorVTInfo<v8f16, v4f32, v8i1, v4i1, 0b01, "f", ?>;
478 def MVE_URSHR : MVE_ScalarShiftSRegImm<"urshr", 0b01>;
581 def MVE_LSRL : MVE_ScalarShiftDRegImm<"lsrl", 0b01, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
591 def MVE_URSHRL : MVE_ScalarShiftDRegImm<"urshrl", 0b01, 0b1>;
671 let Inst{17-16} = 0b01;
770 let Inst{17-16} = 0b01;
834 "$RdaDest = $RdaSrc", !if(sz, 0b01, 0b10), pattern> {
[all …]
H A DARMInstrThumb2.td749 let Inst{26-25} = 0b01;
773 let Inst{26-25} = 0b01;
846 let Inst{26-25} = 0b01;
859 let Inst{26-25} = 0b01;
936 let Inst{25-24} = 0b01;
1002 let Inst{26-25} = 0b01;
1016 let Inst{26-25} = 0b01;
1045 let Inst{26-25} = 0b01;
1058 let Inst{26-25} = 0b01;
1163 let Inst{26-25} = 0b01;
[all …]
/freebsd/sys/arm/ti/am335x/
H A Dtps65217x.h96 #define TPS65217_VO_415V 0b01
/freebsd/contrib/llvm-project/libc/src/__support/threads/linux/
H A Draw_mutex.h43 LIBC_INLINE_VAR static constexpr FutexWordType LOCKED = 0b01;
/freebsd/sys/cddl/dev/kinst/riscv/
H A Dkinst_isa.c175 case 0b01: in kinst_emulate()
387 case 0b01: in kinst_instr_dissect()
/freebsd/crypto/openssl/test/
H A Dsanitytest.c50 b01, in test_sanity_enum_size() enumerator

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