Lines Matching refs:b01
1942 let Inst{20-19} = 0b01;
1957 let Inst{20-19} = 0b01;
3610 let Inst{25-24} = 0b01;
4465 let Inst{11-10} = 0b01;
4835 : BaseMemTag<0b01, 0b00, asm_insn, asm_opnds, "$Rt = $wback",
4869 BaseMemTagStore<opc1, 0b01, insn, "\t$Rt, [$Rn], $offset",
4984 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
4990 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
5035 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
5044 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
5107 let Inst{23-22} = 0b01; // 64-bit FPR flag
5123 let Inst{23-22} = 0b01; // 64-bit FPR flag
5151 let Inst{23-22} = 0b01; // 64-bit FPR flag
5177 let Inst{23-22} = 0b01; // 64-bit FPR flag
5269 let Inst{23-22} = 0b01; // 64-bit FPR flag
5291 let Inst{23-22} = 0b01; // 64-bit FPR flag
5294 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
5300 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
5329 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
5333 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
5337 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
5345 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
5387 let Inst{23-22} = 0b01; // 64-bit size flag
5405 let Inst{23-22} = 0b01; // 64-bit registers
5453 let Inst{23-22} = 0b01; // 64-bit size flag
5472 let Inst{23-22} = 0b01; // 64-bit size flag
5518 let Inst{23-22} = 0b01; // 64-bit size flag
5626 let Inst{23-22} = 0b01;
5631 let Inst{23-22} = 0b01;
5658 let Inst{11-10} = 0b01;
5682 let Inst{23-22} = 0b01;
5723 let Inst{23-22} = 0b01;
5756 let Inst{23-22} = 0b01;
5977 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
5980 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
6000 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
6003 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
6024 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0b01}, {0b11,opc}, V64,
6028 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0b01}, {0b11,opc}, V128,
6207 def v8f8 : BaseSIMDThreeVectors<0b0, 0b0, 0b01, 0b1110, V64, V64, asm, ".8b",".4h">;
6208 def v16f8 : BaseSIMDThreeVectors<0b1, 0b0, 0b01, 0b1110, V128, V128, asm, ".16b", ".8h">;
6221 def v4f16 : BaseSIMDThreeSameVectorDot<0b0, 0b0, 0b01, 0b1111, asm, ".4h", ".8b",
6223 def v8f16 : BaseSIMDThreeSameVectorDot<0b1, 0b0, 0b01, 0b1111, asm, ".8h", ".16b",
6296 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
6299 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
6334 def v4i16 : BaseSIMDVectorLShiftLongBySize<0, 0b01, V64,
6336 def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128,
6354 def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
6357 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
6378 def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, 0b00, V64,
6382 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128,
6405 def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, 0b00, V64,
6408 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, 0b00, V128,
6430 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
6433 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
6469 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, 0b00, V64,
6472 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, 0b00, V128,
6635 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
6638 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
6701 def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, 0b00, opc, V64,
6704 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, 0b00, opc, V128,
7327 let Inst{31-30} = 0b01;
7347 let Inst{31-30} = 0b01;
7390 def v1i16: BaseSIMDThreeScalarTied<U, 0b01, R, opc, (outs FPR16:$dst),
7402 def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
7420 def NAME#32 : BaseSIMDThreeScalar<U, {S,0b01}, {0b11,opc}, FPR32, asm,
7440 let Inst{31-30} = 0b01;
7455 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
7467 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
7492 let Inst{31-30} = 0b01;
7514 let Inst{31-30} = 0b01;
7534 let Inst{31-30} = 0b01;
7637 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR16, asm, []>;
7652 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
7667 def v1i16 : BaseSIMDTwoScalar<U, 0b01, 0b00, opc, FPR16, FPR32, asm, []>;
7684 let Inst{31-30} = 0b01;
7743 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR16, V64,
7745 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
7756 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64,
7758 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
8146 def v8i8Two : BaseSIMDTableLookup<0, 0b01, op, V64, VecListTwo16b,
8154 def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b,
8190 def v8i8Two : BaseSIMDTableLookupTied<0, 0b01, op, V64, VecListTwo16b,
8198 def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b,
8270 …def v16f8 : BaseSIMDTableLookupIndexed<0b1, {0b01,?,0b10}, V128, VecListOne16b, VectorIndexD, asm,…
8274 …def v8f16 : BaseSIMDTableLookupIndexed<0b1, {0b01,?,?,0b1}, V128, VecListTwo8h, VectorIndexS, asm,…
8605 : BaseSIMDIndexedTied<Q, U, 0b0, 0b01, 0b1111,
8811 def v4f16 : BaseSIMDThreeSameVectorIndexH<0b0, 0b0, 0b01, 0b0000, asm, ".4h", ".8b", ".2b",
8813 def v8f16 : BaseSIMDThreeSameVectorIndexH<0b1, 0b0, 0b01, 0b0000, asm, ".8h", ".16b", ".2b",
9160 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64,
9172 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
9209 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
9233 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
9246 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
9286 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64,
9298 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
9338 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
9351 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
9389 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
9409 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
9425 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
9468 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
9521 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
9534 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
9577 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
9590 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
9645 let Inst{31-30} = 0b01;
9665 let Inst{31-30} = 0b01;
10440 def v8h : BaseSIMDLdSt<1, 1, opcode, 0b01, asm,
10452 def v4h : BaseSIMDLdSt<0, 1, opcode, 0b01, asm,
10465 def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm,
10485 def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm,
10513 def v8h : BaseSIMDLdSt<1, 0, opcode, 0b01, asm, (outs),
10525 def v4h : BaseSIMDLdSt<0, 0, opcode, 0b01, asm, (outs),
10537 def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm,
10557 def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm,
10766 def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm,
10768 def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm,
10785 def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm,
10788 def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm,
11211 def v4i16 : BaseSIMDThreeSameVectorTiedR0<0, U, 0b01, opc, V64, asm, ".4h",
11214 def v8i16 : BaseSIMDThreeSameVectorTiedR0<1, U, 0b01, opc, V128, asm, ".8h",
11227 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
11240 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
11276 def v1i16_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
11356 def v4f16 : BaseSIMDThreeSameVectorComplex<0, U, 0b01, opcode, V64, rottype,
11363 def v8f16 : BaseSIMDThreeSameVectorComplex<1, U, 0b01, opcode, V128, rottype,
11428 def v4f16 : BaseSIMDThreeSameVectorTiedComplex<0, U, 0b01, opcode, V64,
11435 def v8f16 : BaseSIMDThreeSameVectorTiedComplex<1, U, 0b01, opcode, V128,
11510 def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64,
11518 def v8f16_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b01, opc1, opc2,
11796 let Sz = 0b01, Acq = Acq, Rel = Rel in def H : BaseCAS<order, "h", GPR32>;
11812 let Sz = 0b01, Acq = Acq, Rel = Rel in
11844 let Sz = 0b01, Acq = Acq, Rel = Rel in def H : BaseSWP<order, "h", GPR32>;
11879 let Sz = 0b01, Acq = Acq, Rel = Rel, opc = opc in
12032 let Inst{25-24} = 0b01;
12038 let Inst{11-10} = 0b01;
12070 let Inst{11-10} = 0b01;
12087 def WN : MOPSMemoryCopy<opcode, 0b00, 0b01, asm # "wn">;
12090 def WT : MOPSMemoryCopy<opcode, 0b01, 0b00, asm # "wt">;
12091 def WTWN : MOPSMemoryCopy<opcode, 0b01, 0b01, asm # "wtwn">;
12092 def WTRN : MOPSMemoryCopy<opcode, 0b01, 0b10, asm # "wtrn">;
12093 def WTN : MOPSMemoryCopy<opcode, 0b01, 0b11, asm # "wtn">;
12095 def RTWN : MOPSMemoryCopy<opcode, 0b10, 0b01, asm # "rtwn">;
12099 def TWN : MOPSMemoryCopy<opcode, 0b11, 0b01, asm # "twn">;
12106 def WN : MOPSMemoryMove<opcode, 0b00, 0b01, asm # "wn">;
12109 def WT : MOPSMemoryMove<opcode, 0b01, 0b00, asm # "wt">;
12110 def WTWN : MOPSMemoryMove<opcode, 0b01, 0b01, asm # "wtwn">;
12111 def WTRN : MOPSMemoryMove<opcode, 0b01, 0b10, asm # "wtrn">;
12112 def WTN : MOPSMemoryMove<opcode, 0b01, 0b11, asm # "wtn">;
12114 def RTWN : MOPSMemoryMove<opcode, 0b10, 0b01, asm # "rtwn">;
12118 def TWN : MOPSMemoryMove<opcode, 0b11, 0b01, asm # "twn">;
12265 let Inst{11-10} = 0b01; // size
12278 let Inst{20-19} = 0b01;
12322 let Inst{12-11} = 0b01;
12515 let Inst{20-19} = 0b01;