1647cbc5dSDimitry Andric//===-- RISCVInstrInfoZcmop.td -----------------------------*- tablegen -*-===// 2647cbc5dSDimitry Andric// 3647cbc5dSDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4647cbc5dSDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5647cbc5dSDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6647cbc5dSDimitry Andric// 7647cbc5dSDimitry Andric//===----------------------------------------------------------------------===// 8647cbc5dSDimitry Andric// 9647cbc5dSDimitry Andric// This file describes the RISC-V instructions from the standard Compressed 10647cbc5dSDimitry Andric// May-Be-Operations Extension (Zcmop). 11647cbc5dSDimitry Andric// 12647cbc5dSDimitry Andric//===----------------------------------------------------------------------===// 13647cbc5dSDimitry Andric 14647cbc5dSDimitry Andriclet hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 15647cbc5dSDimitry Andricclass CMOPInst<bits<3> imm3, string opcodestr> 16647cbc5dSDimitry Andric : RVInst16CI<0b011, 0b01, (outs), (ins), opcodestr, ""> { 17647cbc5dSDimitry Andric let Inst{6-2} = 0; 18647cbc5dSDimitry Andric let Inst{7} = 1; 19647cbc5dSDimitry Andric let Inst{10-8} = imm3; 20647cbc5dSDimitry Andric let Inst{12-11} = 0; 21647cbc5dSDimitry Andric} 22647cbc5dSDimitry Andric 23*0fca6ea1SDimitry Andricforeach n = [1, 3, 5, 7, 9, 11, 13, 15] in { 24647cbc5dSDimitry Andric let Predicates = [HasStdExtZcmop] in 25*0fca6ea1SDimitry Andric def C_MOP # n : CMOPInst<!srl(n, 1), "c.mop." # n>, Sched<[]>; 26647cbc5dSDimitry Andric} 27