Lines Matching refs:b01
749 let Inst{26-25} = 0b01;
773 let Inst{26-25} = 0b01;
846 let Inst{26-25} = 0b01;
859 let Inst{26-25} = 0b01;
936 let Inst{25-24} = 0b01;
1002 let Inst{26-25} = 0b01;
1016 let Inst{26-25} = 0b01;
1045 let Inst{26-25} = 0b01;
1058 let Inst{26-25} = 0b01;
1161 let Inst{26-25} = 0b01;
1176 let Inst{26-25} = 0b01;
1462 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1468 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
1554 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1560 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1578 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
1584 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
1663 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
1665 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
1692 def t2LDAH : T2Ildacq<0b1101, 0b01, (outs rGPR:$Rt),
1700 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si,
1721 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb),
1747 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb),
1849 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>;
1905 def t2STLH : T2Istrrel<0b01, (outs), (ins rGPR:$Rt, addr_offset_none:$addr),
2061 let Inst{24-23} = 0b01; // Increment After
2076 let Inst{24-23} = 0b01; // Increment After
2130 let Inst{24-23} = 0b01; // Increment After
2148 let Inst{24-23} = 0b01; // Increment After
2211 let Inst{26-25} = 0b01;
2773 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, srl>;
2793 let Inst{26-25} = 0b01;
2810 let Inst{26-25} = 0b01;
2814 let Inst{5-4} = 0b01; // Shift type.
2817 let Inst{7-6} = 0b01;
2825 let Inst{26-25} = 0b01;
2832 let Inst{7-6} = 0b01;
2979 let Inst{26-25} = 0b01;
2992 let Inst{26-25} = 0b01;
3140 def t2SMULBT : T2ThreeRegSMUL<0b001, 0b01, "smulbt",
3148 def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt",
3186 def t2SMLABT : T2FourRegSMLA<0b001, 0b01, "smlabt",
3194 def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt",
3344 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3349 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3353 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3361 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
3379 let Inst{26-25} = 0b01;
3408 let Inst{26-25} = 0b01;
3456 def t2CRC32H : T2I_crc32<0, 0b01, "h", int_arm_crc32h>;
3457 def t2CRC32CH : T2I_crc32<1, 0b01, "ch", int_arm_crc32ch>;
3495 let Inst{26-25} = 0b01;
3511 let Inst{26-25} = 0b01;
4205 def t2DCPS1 : T2DCPS<0b01, "dcps1">;
4830 def t2TTT : T2TT<0b01, "ttt",