1//===-- RISCVInstrInfoP.td - RISC-V 'P' instructions -------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instructions from the standard 'Base P' 10// Packed SIMD instruction set extension. 11// 12// This version is still experimental as the 'P' extension hasn't been 13// ratified yet. 14// 15//===----------------------------------------------------------------------===// 16 17//===----------------------------------------------------------------------===// 18// Operand and SDNode transformation definitions. 19//===----------------------------------------------------------------------===// 20 21def simm10 : RISCVSImmLeafOp<10>; 22 23def SImm10UnsignedAsmOperand : SImmAsmOperand<10, "Unsigned"> { 24 let RenderMethod = "addSImm10UnsignedOperands"; 25} 26 27// A 10-bit signed immediate allowing range [-512, 1023] 28// but represented as [-512, 511]. 29def simm10_unsigned : RISCVOp { 30 let ParserMatchClass = SImm10UnsignedAsmOperand; 31 let EncoderMethod = "getImmOpValue"; 32 let DecoderMethod = "decodeSImmOperand<10>"; 33 let OperandType = "OPERAND_SIMM10"; 34 let MCOperandPredicate = [{ 35 int64_t Imm; 36 if (!MCOp.evaluateAsConstantImm(Imm)) 37 return false; 38 return isInt<10>(Imm); 39 }]; 40} 41 42//===----------------------------------------------------------------------===// 43// Instruction class templates 44//===----------------------------------------------------------------------===// 45 46let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 47class RVPUnaryImm10<bits<7> funct7, string opcodestr, 48 DAGOperand TyImm10 = simm10> 49 : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins TyImm10:$imm10), 50 opcodestr, "$rd, $imm10"> { 51 bits<10> imm10; 52 53 let Inst{31-25} = funct7; 54 let Inst{24-16} = imm10{8-0}; 55 let Inst{15} = imm10{9}; 56} 57 58let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 59class RVPUnaryImm8<bits<8> funct8, string opcodestr> 60 : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins uimm8:$uimm8), 61 opcodestr, "$rd, $uimm8"> { 62 bits<8> uimm8; 63 64 let Inst{31-24} = funct8; 65 let Inst{23-16} = uimm8; 66 let Inst{15} = 0b0; 67} 68 69let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 70class RVPUnary<bits<3> f, string opcodestr, dag operands, string argstr> 71 : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), operands, opcodestr, argstr> { 72 bits<5> imm; 73 bits<5> rs1; 74 75 let Inst{31} = 0b1; 76 let Inst{30-28} = f; 77 let Inst{27} = 0b0; 78 let Inst{19-15} = rs1; 79} 80 81class RVPUnaryImm5<bits<3> f, string opcodestr> 82 : RVPUnary<f, opcodestr, (ins GPR:$rs1, uimm5:$uimm5), "$rd, $rs1, $uimm5"> { 83 bits<5> uimm5; 84 85 let imm = uimm5; 86 let Inst{26-25} = 0b01; 87 let Inst{24-20} = uimm5; 88} 89 90class RVPUnaryImm4<bits<3> f, string opcodestr> 91 : RVPUnary<f, opcodestr, (ins GPR:$rs1, uimm4:$uimm4), "$rd, $rs1, $uimm4"> { 92 bits<4> uimm4; 93 94 let Inst{26-24} = 0b001; 95 let Inst{23-20} = uimm4; 96} 97 98class RVPUnaryImm3<bits<3> f, string opcodestr> 99 : RVPUnary<f, opcodestr, (ins GPR:$rs1, uimm3:$uimm3), "$rd, $rs1, $uimm3"> { 100 bits<3> uimm3; 101 102 let Inst{26-23} = 0b0001; 103 let Inst{22-20} = uimm3; 104} 105 106let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in 107class RVPUnaryWUF<bits<2> w, bits<5> uf, string opcodestr> 108 : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins GPR:$rs1), 109 opcodestr, "$rd, $rs1"> { 110 let Inst{31-27} = 0b11100; 111 let Inst{26-25} = w; 112 let Inst{24-20} = uf; 113} 114 115//===----------------------------------------------------------------------===// 116// Instructions 117//===----------------------------------------------------------------------===// 118 119let Predicates = [HasStdExtP] in { 120def CLS : Unary_r<0b011000000011, 0b001, "cls">; 121def ABS : Unary_r<0b011000000111, 0b001, "abs">; 122} // Predicates = [HasStdExtP] 123let Predicates = [HasStdExtP, IsRV32] in 124def REV_RV32 : Unary_r<0b011010011111, 0b101, "rev">; 125 126let Predicates = [HasStdExtP, IsRV64] in { 127def REV16 : Unary_r<0b011010110000, 0b101, "rev16">; 128def REV_RV64 : Unary_r<0b011010111111, 0b101, "rev">; 129 130def CLSW : UnaryW_r<0b011000000011, 0b001, "clsw">; 131def ABSW : UnaryW_r<0b011000000111, 0b001, "absw">; 132} // Predicates = [HasStdExtP, IsRV64] 133 134let Predicates = [HasStdExtP] in { 135def PSLLI_B : RVPUnaryImm3<0b000, "pslli.b">; 136def PSLLI_H : RVPUnaryImm4<0b000, "pslli.h">; 137def PSSLAI_H : RVPUnaryImm4<0b101, "psslai.h">; 138} // Predicates = [HasStdExtP] 139let DecoderNamespace = "RV32Only", 140 Predicates = [HasStdExtP, IsRV32] in 141def SSLAI : RVPUnaryImm5<0b101, "sslai">; 142let Predicates = [HasStdExtP, IsRV64] in { 143def PSLLI_W : RVPUnaryImm5<0b000, "pslli.w">; 144def PSSLAI_W : RVPUnaryImm5<0b101, "psslai.w">; 145} // Predicates = [HasStdExtP, IsRV64] 146 147let Predicates = [HasStdExtP] in 148def PLI_H : RVPUnaryImm10<0b1011000, "pli.h">; 149let Predicates = [HasStdExtP, IsRV64] in 150def PLI_W : RVPUnaryImm10<0b1011001, "pli.w">; 151let Predicates = [HasStdExtP] in 152def PLI_B : RVPUnaryImm8<0b10110100, "pli.b">; 153 154let Predicates = [HasStdExtP] in { 155def PSEXT_H_B : RVPUnaryWUF<0b00, 0b00100, "psext.h.b">; 156def PSABS_H : RVPUnaryWUF<0b00, 0b00111, "psabs.h">; 157def PSABS_B : RVPUnaryWUF<0b10, 0b00111, "psabs.b">; 158} // Predicates = [HasStdExtP] 159let Predicates = [HasStdExtP, IsRV64] in { 160def PSEXT_W_B : RVPUnaryWUF<0b01, 0b00100, "psext.w.b">; 161def PSEXT_W_H : RVPUnaryWUF<0b01, 0b00101, "psext.w.h">; 162} // Predicates = [HasStdExtP, IsRV64] 163 164let Predicates = [HasStdExtP] in 165def PLUI_H : RVPUnaryImm10<0b1111000, "plui.h", simm10_unsigned>; 166let Predicates = [HasStdExtP, IsRV64] in 167def PLUI_W : RVPUnaryImm10<0b1111001, "plui.w", simm10_unsigned>; 168