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Searched refs:DestReg (Results 1 – 25 of 147) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumbRegisterInfo.cpp61 const DebugLoc &dl, unsigned DestReg, in emitThumb1LoadConstPool() argument
74 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
81 const DebugLoc &dl, unsigned DestReg, in emitThumb2LoadConstPool() argument
93 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
103 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
108 assert((DestReg.isVirtual() || isARMLowRegister(DestReg)) && in emitLoadConstPool()
110 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
113 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
124 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
132 (DestReg.isVirtual() || isARMLowRegister(DestReg)) && NumBytes >= 0 && in emitThumbRegPlusImmInReg()
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H A DThumb1InstrInfo.cpp44 const DebugLoc &DL, Register DestReg, in copyPhysReg() argument
51 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
55 !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
56 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
71 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg) in copyPhysReg()
99 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
111 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
146 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, in loadRegFromStackSlot() argument
150 (DestReg.isPhysical() && isARMLowRegister(DestReg))) && in loadRegFromStackSlot()
154 (DestReg.isPhysical() && isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
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H A DThumb2InstrInfo.cpp134 Register DestReg = MI.getOperand(0).getReg(); in optimizeSelect() local
136 if (!DestReg.isVirtual()) in optimizeSelect()
140 get(ARM::t2CSEL), DestReg) in optimizeSelect()
152 const DebugLoc &DL, Register DestReg, in copyPhysReg() argument
156 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
157 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
159 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
211 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, in loadRegFromStackSlot() argument
223 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
235 if (DestReg.isVirtual()) { in loadRegFromStackSlot()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZPostRewrite.cpp81 Register DestReg = MBBI->getOperand(0).getReg(); in selectLOCRMux() local
83 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectLOCRMux()
102 Register DestReg = MBBI->getOperand(0).getReg(); in selectSELRMux() local
107 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectSELRMux()
120 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
130 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
133 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
135 Src1MO.setReg(DestReg); in selectSELRMux()
136 Src1Reg = DestReg; in selectSELRMux()
140 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp437 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, in loadRegFromStackSlot() argument
471 BuildMI(MBB, I, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
479 const DebugLoc &DL, Register DestReg, in copyPhysReg() argument
483 CSKY::CARRYRegClass.contains(DestReg)) { in copyPhysReg()
485 BuildMI(MBB, I, DL, get(CSKY::BTSTI32), DestReg) in copyPhysReg()
490 BuildMI(MBB, I, DL, get(CSKY::BTSTI16), DestReg) in copyPhysReg()
498 CSKY::GPRRegClass.contains(DestReg)) { in copyPhysReg()
501 BuildMI(MBB, I, DL, get(CSKY::MVC32), DestReg) in copyPhysReg()
504 assert(DestReg < CSKY::R16); in copyPhysReg()
505 assert(DestReg < CSKY::R8); in copyPhysReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp263 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() local
275 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)), DestReg) in doAtomicBinOpExpansion()
282 .addReg(DestReg) in doAtomicBinOpExpansion()
299 MachineBasicBlock *MBB, Register DestReg, in insertMaskedMerge() argument
315 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
328 Register DestReg = MI.getOperand(0).getReg(); in doMaskedAtomicBinOpExpansion() local
344 BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering, STI)), DestReg) in doMaskedAtomicBinOpExpansion()
356 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
361 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
366 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
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H A DRISCVRegisterInfo.cpp196 const DebugLoc &DL, Register DestReg, in adjustReg() argument
201 if (DestReg == SrcReg && !Offset.getFixed() && !Offset.getScalable()) in adjustReg()
236 Register ScratchReg = DestReg; in adjustReg()
237 if (DestReg == SrcReg) in adjustReg()
258 BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg) in adjustReg()
277 BuildMI(MBB, II, DL, TII->get(Opc), DestReg) in adjustReg()
283 BuildMI(MBB, II, DL, TII->get(ScalableAdjOpc), DestReg) in adjustReg()
289 SrcReg = DestReg; in adjustReg()
294 if (DestReg == SrcReg && Val == 0) in adjustReg()
300 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
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H A DRISCVMergeBaseOffset.cpp320 Register DestReg = Lo.getOperand(0).getReg(); in detectAndFoldOffset() local
325 if (!MRI->hasOneUse(DestReg)) in detectAndFoldOffset()
329 MachineInstr &Tail = *MRI->use_instr_begin(DestReg); in detectAndFoldOffset()
365 return foldLargeOffset(Hi, Lo, Tail, DestReg); in detectAndFoldOffset()
372 return foldShiftedOffset(Hi, Lo, Tail, DestReg); in detectAndFoldOffset()
380 Register DestReg = Lo.getOperand(0).getReg(); in foldIntoMemoryOps() local
397 for (const MachineInstr &UseMI : MRI->use_instructions(DestReg)) { in foldIntoMemoryOps()
428 if (DestReg == UseMI.getOperand(0).getReg()) in foldIntoMemoryOps()
430 assert(DestReg == UseMI.getOperand(1).getReg() && in foldIntoMemoryOps()
459 if (MO.isReg() && MO.getReg() == DestReg) in foldIntoMemoryOps()
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H A DRISCVMoveMerger.cpp194 Register DestReg = SecondPair->Destination->getReg(); in findMatchingInst() local
198 if ((RegPair.Destination->getReg() == DestReg)) in findMatchingInst()
204 if (!ModifiedRegUnits.available(DestReg) || in findMatchingInst()
205 !UsedRegUnits.available(DestReg) || in findMatchingInst()
213 (RegPair.Destination->getReg() == DestReg)) in findMatchingInst()
216 if (!ModifiedRegUnits.available(DestReg) || in findMatchingInst()
217 !UsedRegUnits.available(DestReg) || in findMatchingInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp131 void emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg,
866 void LoongArchAsmParser::emitLAInstSeq(MCRegister DestReg, MCRegister TmpReg, in emitLAInstSeq() argument
882 Out.emitInstruction(MCInstBuilder(Opc).addReg(DestReg).addExpr(LE), in emitLAInstSeq()
891 MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addImm(0), in emitLAInstSeq()
897 .addReg(DestReg) in emitLAInstSeq()
903 MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addExpr(LE), in emitLAInstSeq()
909 .addReg(DestReg == TmpReg ? DestReg : TmpReg) in emitLAInstSeq()
910 .addReg(DestReg == TmpReg ? DestReg : TmpReg) in emitLAInstSeq()
923 .addReg(DestReg == TmpReg ? TmpReg : LoongArch::R0) in emitLAInstSeq()
930 MCInstBuilder(Opc).addReg(DestReg).addReg(DestReg).addReg(TmpReg), in emitLAInstSeq()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp406 Register DestReg = I->getOperand(0).getReg(); in searchALUInst() local
418 if (Opnd.getReg() == DestReg) { in searchALUInst()
439 if (TRI->regsOverlap(DestReg, Opnd.getReg())) in searchALUInst()
564 Register DestReg = MI.getOperand(0).getReg(); in optTwoAddrLEA() local
569 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
586 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
588 if (DestReg != BaseReg) in optTwoAddrLEA()
593 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
598 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
601 } else if (DestReg == BaseReg && !IndexReg) { in optTwoAddrLEA()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp178 bool emitCmp(unsigned DestReg, const CmpInst *CI);
182 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
185 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
187 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
189 unsigned DestReg);
191 unsigned DestReg);
388 Register DestReg = createResultReg(RC); in materializeFP() local
390 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
391 return DestReg; in materializeFP()
394 Register DestReg = createResultReg(RC); in materializeFP() local
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H A DMipsSEInstrInfo.cpp82 const DebugLoc &DL, Register DestReg, in copyPhysReg() argument
88 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
109 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
117 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
119 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
121 else if (Mips::HI32RegClass.contains(DestReg)) in copyPhysReg()
122 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
123 else if (Mips::LO32RegClass.contains(DestReg)) in copyPhysReg()
124 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
125 else if (Mips::HI32DSPRegClass.contains(DestReg)) in copyPhysReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp438 const DebugLoc &DL, Register DestReg, in copyPhysReg() argument
453 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
454 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
456 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
461 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
462 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
464 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
466 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
474 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
477 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp168 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() local
179 TII->get(Width == 32 ? LoongArch::LL_W : LoongArch::LL_D), DestReg) in doAtomicBinOpExpansion()
192 .addReg(DestReg) in doAtomicBinOpExpansion()
200 .addReg(DestReg) in doAtomicBinOpExpansion()
205 .addReg(DestReg) in doAtomicBinOpExpansion()
210 .addReg(DestReg) in doAtomicBinOpExpansion()
215 .addReg(DestReg) in doAtomicBinOpExpansion()
220 .addReg(DestReg) in doAtomicBinOpExpansion()
236 MachineBasicBlock *MBB, Register DestReg, in insertMaskedMerge() argument
250 BuildMI(MBB, DL, TII->get(LoongArch::XOR), DestReg) in insertMaskedMerge()
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H A DLoongArchExpandPseudoInsts.cpp73 const MachineOperand &Symbol, Register DestReg,
191 Register DestReg = MI.getOperand(0).getReg(); in expandPcalau12iInstPair() local
200 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg) in expandPcalau12iInstPair()
224 unsigned IdentifyingMO, const MachineOperand &Symbol, Register DestReg, in expandLargeAddressLoad() argument
271 DestReg.isVirtual() in expandLargeAddressLoad()
273 : DestReg; in expandLargeAddressLoad()
275 DestReg.isVirtual() in expandLargeAddressLoad()
277 : DestReg; in expandLargeAddressLoad()
279 DestReg.isVirtual() in expandLargeAddressLoad()
281 : DestReg; in expandLargeAddressLoad()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineScheduler.cpp264 Register DestReg = MI->getOperand(0).getReg(); in getAluKind() local
265 if (regBelongsToClass(DestReg, &R600::R600_TReg32_XRegClass) || in getAluKind()
266 regBelongsToClass(DestReg, &R600::R600_AddrRegClass)) in getAluKind()
268 if (regBelongsToClass(DestReg, &R600::R600_TReg32_YRegClass)) in getAluKind()
270 if (regBelongsToClass(DestReg, &R600::R600_TReg32_ZRegClass)) in getAluKind()
272 if (regBelongsToClass(DestReg, &R600::R600_TReg32_WRegClass)) in getAluKind()
274 if (regBelongsToClass(DestReg, &R600::R600_Reg128RegClass)) in getAluKind()
350 Register DestReg = MI->getOperand(DstIndex).getReg(); in AssignSlot() local
354 if (MO.getReg() == DestReg) in AssignSlot()
359 MRI->constrainRegClass(DestReg, &R600::R600_TReg32_XRegClass); in AssignSlot()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp142 inline MachineInstrBuilder build(const MCInstrDesc &MCID, Register DestReg) { in build() argument
143 return BuildMI(MBB, II, DL, MCID, DestReg); in build()
145 inline MachineInstrBuilder build(unsigned InstOpc, Register DestReg) { in build() argument
146 return build(get(InstOpc), DestReg); in build()
260 Register DestReg = MI.getOperand(0).getReg(); in processLDQ() local
261 Register DestHiReg = getSubReg(DestReg, VE::sub_even); in processLDQ()
262 Register DestLoReg = getSubReg(DestReg, VE::sub_odd); in processLDQ()
330 Register DestReg = MI.getOperand(0).getReg(); in processLDVM() local
348 build(VE::LVMir, DestReg).addImm(i).addReg(TmpReg, getKillRegState(true)); in processLDVM()
350 build(VE::LVMir_m, DestReg) in processLDVM()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitConst32AndConst64.cpp69 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
72 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg) in runOnMachineFunction()
76 Register DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
79 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo); in runOnMachineFunction()
80 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp33 const DebugLoc &DL, Register DestReg, in copyPhysReg() argument
36 if (BPF::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
37 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
39 else if (BPF::GPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
40 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg) in copyPhysReg()
151 MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Register DestReg, in loadRegFromStackSlot() argument
159 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
161 BuildMI(MBB, I, DL, get(BPF::LDW32), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp612 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
615 << printReg(DestReg, TRI) << " at " << *MI); in scanInstruction()
617 auto G = std::make_unique<Chain>(MI, Idx, getColor(DestReg)); in scanInstruction()
618 ActiveChains[DestReg] = G.get(); in scanInstruction()
625 Register DestReg = MI->getOperand(0).getReg(); in scanInstruction() local
630 if (DestReg != AccumReg) in scanInstruction()
645 ActiveChains[AccumReg]->add(MI, Idx, getColor(DestReg)); in scanInstruction()
647 if (DestReg != AccumReg) { in scanInstruction()
648 ActiveChains[DestReg] = ActiveChains[AccumReg]; in scanInstruction()
661 << printReg(DestReg, TRI) << "\n"); in scanInstruction()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h383 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
387 .addReg(DestReg, RegState::Define); in BuildMI()
396 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
403 .addReg(DestReg, RegState::Define); in BuildMI()
415 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
422 .addReg(DestReg, RegState::Define); in BuildMI()
427 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
432 DestReg); in BuildMI()
433 return BuildMI(BB, MachineBasicBlock::iterator(I), MIMD, MCID, DestReg); in BuildMI()
438 const MCInstrDesc &MCID, Register DestReg) { in BuildMI() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.cpp38 const DebugLoc &DL, Register DestReg, in copyPhysReg() argument
44 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
47 if (STI.hasMOVW() && AVR::DREGSMOVWRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
48 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg) in copyPhysReg()
53 TRI.splitReg(DestReg, DestLo, DestHi); in copyPhysReg()
74 if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
76 } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) { in copyPhysReg()
78 } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) { in copyPhysReg()
84 BuildMI(MBB, MI, DL, get(Opc), DestReg) in copyPhysReg()
162 Register DestReg, int FrameIndex, in loadRegFromStackSlot() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrInfo.cpp59 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, Register DestReg, in loadRegFromStackSlot() argument
74 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
78 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
86 const DebugLoc &DL, Register DestReg, in copyPhysReg() argument
90 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
92 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
97 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrInfo.cpp59 const DebugLoc &DL, Register DestReg, in copyPhysReg() argument
67 DestReg.isVirtual() in copyPhysReg()
68 ? MRI.getRegClass(DestReg) in copyPhysReg()
69 : MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(DestReg); in copyPhysReg()
73 BuildMI(MBB, I, DL, get(CopyOpcode), DestReg) in copyPhysReg()

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