135     Register DestReg = MI.getOperand(0).getReg();  in optimizeSelect()  local
137     if (!DestReg.isVirtual())  in optimizeSelect()
141                                         get(ARM::t2CSEL), DestReg)  in optimizeSelect()
153                                   const DebugLoc &DL, MCRegister DestReg,  in copyPhysReg()  argument
156   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))  in copyPhysReg()
157     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);  in copyPhysReg()
159   BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)  in copyPhysReg()
211                                            Register DestReg, int FI,  in loadRegFromStackSlot()  argument
224     BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)  in loadRegFromStackSlot()
236     if (DestReg.isVirtual()) {  in loadRegFromStackSlot()
238       MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass);  in loadRegFromStackSlot()
242     AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
243     AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);  in loadRegFromStackSlot()
246     if (DestReg.isPhysical())  in loadRegFromStackSlot()
247       MIB.addReg(DestReg, RegState::ImplicitDefine);  in loadRegFromStackSlot()
251   ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI,  in loadRegFromStackSlot()
311                                   const DebugLoc &dl, Register DestReg,  in emitT2RegPlusImmediate()  argument
316   if (NumBytes == 0 && DestReg != BaseReg) {  in emitT2RegPlusImmediate()
317     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)  in emitT2RegPlusImmediate()
328   if (DestReg != ARM::SP && DestReg != BaseReg &&  in emitT2RegPlusImmediate()
334       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)  in emitT2RegPlusImmediate()
340       BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)  in emitT2RegPlusImmediate()
341         .addReg(DestReg)  in emitT2RegPlusImmediate()
349         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)  in emitT2RegPlusImmediate()
351             .addReg(DestReg, RegState::Kill)  in emitT2RegPlusImmediate()
361         BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)  in emitT2RegPlusImmediate()
363             .addReg(DestReg, RegState::Kill)  in emitT2RegPlusImmediate()
375     if (DestReg == ARM::SP && BaseReg != ARM::SP) {  in emitT2RegPlusImmediate()
377       BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)  in emitT2RegPlusImmediate()
385     assert((DestReg != ARM::SP || BaseReg == ARM::SP) &&  in emitT2RegPlusImmediate()
389     if ((DestReg == ARM::SP) && (ThisVal < ((1 << 7) - 1) * 4)) {  in emitT2RegPlusImmediate()
392       BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)  in emitT2RegPlusImmediate()
401     bool ToSP = DestReg == ARM::SP;  in emitT2RegPlusImmediate()
427     MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)  in emitT2RegPlusImmediate()
435     BaseReg = DestReg;  in emitT2RegPlusImmediate()