Lines Matching refs:DestReg

407   Register DestReg = I->getOperand(0).getReg();
419         if (Opnd.getReg() == DestReg) {
440         if (TRI->regsOverlap(DestReg, Opnd.getReg()))
565   Register DestReg = MI.getOperand(0).getReg();
570   if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP))
587       (DestReg == BaseReg || DestReg == IndexReg)) {
589     if (DestReg != BaseReg)
594       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
599       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
602   } else if (DestReg == BaseReg && IndexReg == 0) {
616         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
619         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
626         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
630         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
758   Register DestReg = Dest.getReg();
775   if (IsInefficientBase && DestReg == BaseReg && !IsScale1)
782   bool BaseOrIndexIsDst = DestReg == BaseReg || DestReg == IndexReg;
811     if (DestReg != BaseReg)
816       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
822       NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
850         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
851                     .addReg(DestReg);
855         NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
856                     .addReg(DestReg)
869   assert(DestReg != BaseReg && "DestReg == BaseReg should be handled already!");
879     TII->copyPhysReg(MBB, MI, MI.getDebugLoc(), DestReg, BaseReg, BIK);
883     NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
884                 .addReg(DestReg)
906   NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
907               .addReg(DestReg)