Lines Matching refs:DestReg
437 Register DestReg, int FI, in loadRegFromStackSlot() argument
472 BuildMI(MBB, I, DL, get(Opcode), DestReg) in loadRegFromStackSlot()
480 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
483 CSKY::CARRYRegClass.contains(DestReg)) { in copyPhysReg()
485 BuildMI(MBB, I, DL, get(CSKY::BTSTI32), DestReg) in copyPhysReg()
490 BuildMI(MBB, I, DL, get(CSKY::BTSTI16), DestReg) in copyPhysReg()
498 CSKY::GPRRegClass.contains(DestReg)) { in copyPhysReg()
501 BuildMI(MBB, I, DL, get(CSKY::MVC32), DestReg) in copyPhysReg()
504 assert(DestReg < CSKY::R16); in copyPhysReg()
505 assert(DestReg < CSKY::R8); in copyPhysReg()
506 BuildMI(MBB, I, DL, get(CSKY::MOVI16), DestReg).addImm(0); in copyPhysReg()
508 .addReg(DestReg, RegState::Define) in copyPhysReg()
510 .addReg(DestReg, getKillRegState(true)) in copyPhysReg()
511 .addReg(DestReg, getKillRegState(true)) in copyPhysReg()
515 .addReg(DestReg) in copyPhysReg()
522 if (CSKY::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
524 else if (v2sf && CSKY::sFPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
526 else if (v3sf && CSKY::FPR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
528 else if (v2df && CSKY::sFPR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
530 else if (v3df && CSKY::FPR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
533 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
536 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
539 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
542 CSKY::GPRRegClass.contains(DestReg)) in copyPhysReg()
545 CSKY::sFPR32RegClass.contains(DestReg)) in copyPhysReg()
548 CSKY::FPR32RegClass.contains(DestReg)) in copyPhysReg()
551 CSKY::sFPR64RegClass.contains(DestReg)) in copyPhysReg()
554 CSKY::FPR64RegClass.contains(DestReg)) in copyPhysReg()
557 LLVM_DEBUG(dbgs() << "src = " << SrcReg << ", dst = " << DestReg); in copyPhysReg()
562 BuildMI(MBB, I, DL, get(Opcode), DestReg) in copyPhysReg()