| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZSelectionDAGInfo.cpp | 24 static SDValue createMemMemNode(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in createMemMemNode() argument
34 return DAG.getNode(Op, DL, VTs, Ops); in createMemMemNode()
41 static SDValue emitMemMemImm(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in emitMemMemImm() argument
46 SDValue LenAdj = DAG.getConstant(Size - Adj, DL, Dst.getValueType()); in emitMemMemImm()
47 return createMemMemNode(DAG, DL, Op, Chain, Dst, Src, LenAdj, Byte); in emitMemMemImm()
50 static SDValue emitMemMemReg(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in emitMemMemReg() argument
54 SDValue LenAdj = DAG.getNode(ISD::ADD, DL, MVT::i64, in emitMemMemReg()
55 DAG.getZExtOrTrunc(Size, DL, MVT::i64), in emitMemMemReg()
56 DAG.getConstant(0 - Adj, DL, MVT::i64)); in emitMemMemReg()
57 return createMemMemNode(DAG, DL, Op, Chain, Dst, Src, LenAdj, Byte); in emitMemMemReg()
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| H A D | SystemZISelLowering.cpp | 774 EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL, in getSetCCResultType() argument
1082 bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode() argument
1476 static SDValue convertLocVTToValVT(SelectionDAG &DAG, const SDLoc &DL, in convertLocVTToValVT() argument
1482 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1485 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1489 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value); in convertLocVTToValVT()
1495 Value = DAG.getBuildVector(MVT::v2i64, DL, {Value, DAG.getUNDEF(MVT::i64)}); in convertLocVTToValVT()
1496 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value); in convertLocVTToValVT()
1505 static SDValue convertValVTToLocVT(SelectionDAG &DAG, const SDLoc &DL, in convertValVTToLocVT() argument
1509 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | VNCoercion.cpp | 19 const DataLayout &DL) { in canCoerceMustAliasedValueToLoad() argument
31 uint64_t StoreSize = DL.getTypeSizeInBits(StoredTy).getFixedValue(); in canCoerceMustAliasedValueToLoad()
38 if (StoreSize < DL.getTypeSizeInBits(LoadTy).getFixedValue()) in canCoerceMustAliasedValueToLoad()
41 bool StoredNI = DL.isNonIntegralPointerType(StoredTy->getScalarType()); in canCoerceMustAliasedValueToLoad()
42 bool LoadNI = DL.isNonIntegralPointerType(LoadTy->getScalarType()); in canCoerceMustAliasedValueToLoad()
61 if (StoredNI && StoreSize != DL.getTypeSizeInBits(LoadTy).getFixedValue()) in canCoerceMustAliasedValueToLoad()
78 const DataLayout &DL) { in coerceAvailableValueToLoadType() argument
79 assert(canCoerceMustAliasedValueToLoad(StoredVal, LoadedTy, DL) && in coerceAvailableValueToLoadType()
82 StoredVal = ConstantFoldConstant(C, DL); in coerceAvailableValueToLoadType()
87 uint64_t StoredValSize = DL.getTypeSizeInBits(StoredValTy).getFixedValue(); in coerceAvailableValueToLoadType()
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| H A D | Evaluator.cpp | 47 const DataLayout &DL);
60 const DataLayout &DL) { in isSimpleEnoughValueToCommitHelper() argument
73 if (!isSimpleEnoughValueToCommit(cast<Constant>(Op), SimpleConstants, DL)) in isSimpleEnoughValueToCommitHelper()
85 return isSimpleEnoughValueToCommit(CE->getOperand(0), SimpleConstants, DL); in isSimpleEnoughValueToCommitHelper()
91 if (DL.getTypeSizeInBits(CE->getType()) != in isSimpleEnoughValueToCommitHelper()
92 DL.getTypeSizeInBits(CE->getOperand(0)->getType())) in isSimpleEnoughValueToCommitHelper()
94 return isSimpleEnoughValueToCommit(CE->getOperand(0), SimpleConstants, DL); in isSimpleEnoughValueToCommitHelper()
101 return isSimpleEnoughValueToCommit(CE->getOperand(0), SimpleConstants, DL); in isSimpleEnoughValueToCommitHelper()
107 return isSimpleEnoughValueToCommit(CE->getOperand(0), SimpleConstants, DL); in isSimpleEnoughValueToCommitHelper()
115 const DataLayout &DL) { in isSimpleEnoughValueToCommit() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | Loads.cpp | 30 const DataLayout &DL) { in isAligned() argument
31 Align BA = Base->getPointerAlignment(DL); in isAligned()
38 const Value *V, Align Alignment, const APInt &Size, const DataLayout &DL, in isDereferenceableAndAlignedPointer() argument
59 APInt Offset(DL.getIndexTypeSizeInBits(GEP->getType()), 0); in isDereferenceableAndAlignedPointer()
60 if (!GEP->accumulateConstantOffset(DL, Offset) || Offset.isNegative() || in isDereferenceableAndAlignedPointer()
74 Base, Alignment, Offset + Size.sextOrTrunc(Offset.getBitWidth()), DL, in isDereferenceableAndAlignedPointer()
82 BC->getOperand(0), Alignment, Size, DL, CtxI, AC, DT, TLI, in isDereferenceableAndAlignedPointer()
89 Size, DL, CtxI, AC, DT, TLI, in isDereferenceableAndAlignedPointer()
92 Size, DL, CtxI, AC, DT, TLI, in isDereferenceableAndAlignedPointer()
98 V->getPointerDereferenceableBytes(DL, CheckForNonNull, in isDereferenceableAndAlignedPointer()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchExpandAtomicPseudoInsts.cpp | 147 MachineInstr &MI, DebugLoc DL, in doAtomicBinOpExpansion() argument
162 BuildMI(LoopMBB, DL, in doAtomicBinOpExpansion()
170 BuildMI(LoopMBB, DL, TII->get(LoongArch::OR), ScratchReg) in doAtomicBinOpExpansion()
175 BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg) in doAtomicBinOpExpansion()
178 BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg) in doAtomicBinOpExpansion()
183 BuildMI(LoopMBB, DL, TII->get(LoongArch::ADD_W), ScratchReg) in doAtomicBinOpExpansion()
188 BuildMI(LoopMBB, DL, TII->get(LoongArch::SUB_W), ScratchReg) in doAtomicBinOpExpansion()
193 BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg) in doAtomicBinOpExpansion()
198 BuildMI(LoopMBB, DL, TII->get(LoongArch::OR), ScratchReg) in doAtomicBinOpExpansion()
203 BuildMI(LoopMBB, DL, TI in doAtomicBinOpExpansion()
224 insertMaskedMerge(const LoongArchInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register DestReg,Register OldValReg,Register NewValReg,Register MaskReg,Register ScratchReg) insertMaskedMerge() argument
245 doMaskedAtomicBinOpExpansion(const LoongArchInstrInfo * TII,MachineInstr & MI,DebugLoc DL,MachineBasicBlock * ThisMBB,MachineBasicBlock * LoopMBB,MachineBasicBlock * DoneMBB,AtomicRMWInst::BinOp BinOp,int Width) doMaskedAtomicBinOpExpansion() argument
317 DebugLoc DL = MI.getDebugLoc(); expandAtomicBinOp() local
350 insertSext(const LoongArchInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register ValReg,Register ShamtReg) insertSext() argument
370 DebugLoc DL = MI.getDebugLoc(); expandAtomicMinMaxOp() local
496 DebugLoc DL = MI.getDebugLoc(); expandAtomicCmpXchg() local
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| H A D | LoongArchISelLowering.cpp | 464 static SDValue lowerVECTOR_SHUFFLE_VREPLVEI(const SDLoc &DL, ArrayRef<int> Mask, in lowerVECTOR_SHUFFLE_VREPLVEI() argument
481 return DAG.getNode(LoongArchISD::VREPLVEI, DL, VT, V1, in lowerVECTOR_SHUFFLE_VREPLVEI()
482 DAG.getConstant(Imm, DL, MVT::i64)); in lowerVECTOR_SHUFFLE_VREPLVEI()
506 static SDValue lowerVECTOR_SHUFFLE_VSHUF4I(const SDLoc &DL, ArrayRef<int> Mask, in lowerVECTOR_SHUFFLE_VSHUF4I() argument
550 return DAG.getNode(LoongArchISD::VSHUF4I, DL, VT, V1, in lowerVECTOR_SHUFFLE_VSHUF4I()
551 DAG.getConstant(Imm, DL, MVT::i64)); in lowerVECTOR_SHUFFLE_VSHUF4I()
569 static SDValue lowerVECTOR_SHUFFLE_VPACKEV(const SDLoc &DL, ArrayRef<int> Mask, in lowerVECTOR_SHUFFLE_VPACKEV() argument
591 return DAG.getNode(LoongArchISD::VPACKEV, DL, VT, V2, V1); in lowerVECTOR_SHUFFLE_VPACKEV()
609 static SDValue lowerVECTOR_SHUFFLE_VPACKOD(const SDLoc &DL, ArrayRef<int> Mask, in lowerVECTOR_SHUFFLE_VPACKOD() argument
631 return DAG.getNode(LoongArchISD::VPACKOD, DL, VT, V2, V1); in lowerVECTOR_SHUFFLE_VPACKOD()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 371 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn() argument
397 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
400 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
403 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
414 DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64), 0); in LowerReturn()
415 SDValue Sub_f32 = DAG.getTargetConstant(VE::sub_f32, DL, MVT::i32); in LowerReturn()
416 OutVal = SDValue(DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, DL, in LowerReturn()
425 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Glue); in LowerReturn()
438 return DAG.getNode(VEISD::RET_GLUE, DL, MVT::Other, RetOps); in LowerReturn()
443 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 430 SDLoc DL(Op); in LowerOperation() local
436 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
437 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
438 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
439 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
441 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
453 SDLoc DL(Op); in LowerOperation() local
470 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
472 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
473 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
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| H A D | AMDGPUHSAMetadataStreamer.cpp | 27 const DataLayout &DL) { in getArgumentTypeAlign() argument
36 ArgAlign = DL.getABITypeAlign(Ty); in getArgumentTypeAlign()
314 const DataLayout &DL = Func->getDataLayout(); in emitKernelArg() local
328 std::tie(ArgTy, ArgAlign) = getArgumentTypeAlign(Arg, DL); in emitKernelArg()
330 emitKernelArg(DL, ArgTy, ArgAlign, in emitKernelArg()
337 const DataLayout &DL, Type *Ty, Align Alignment, StringRef ValueKind, in emitKernelArg() argument
347 auto Size = DL.getTypeAllocSize(Ty); in emitKernelArg()
395 auto &DL = M->getDataLayout(); in emitHiddenKernelArgs() local
401 emitKernelArg(DL, Int64Ty, Align(8), "hidden_global_offset_x", Offset, in emitHiddenKernelArgs()
404 emitKernelArg(DL, Int64Ty, Align(8), "hidden_global_offset_y", Offset, in emitHiddenKernelArgs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1518 EVT RISCVTargetLowering::getSetCCResultType(const DataLayout &DL, in getSetCCResultType()
1522 return getPointerTy(DL); in getSetCCResultType()
1569 auto &DL = I.getDataLayout(); in getTgtMemIntrinsic()
1594 Info.memVT = getValueType(DL, MemTy); in getTgtMemIntrinsic()
1595 Info.align = Align(DL.getTypeSizeInBits(MemTy->getScalarType()) / 8); in getTgtMemIntrinsic()
1837 bool RISCVTargetLowering::isLegalAddressingMode(const DataLayout &DL, in isLegalAddressingMode()
2387 static void translateSetCCForBranch(const SDLoc &DL, SDValue &LHS, SDValue &RHS, in translateSetCCForBranch()
2406 LHS = DAG.getNode(ISD::SHL, DL, LHS.getValueType(), LHS, in translateSetCCForBranch()
2407 DAG.getConstant(ShAmt, DL, LHS.getValueType())); in translateSetCCForBranch()
2419 RHS = DAG.getConstant(0, DL, RH in translateSetCCForBranch()
1517 getSetCCResultType(const DataLayout & DL,LLVMContext & Context,EVT VT) const getSetCCResultType() argument
1568 auto &DL = I.getDataLayout(); getTgtMemIntrinsic() local
1836 isLegalAddressingMode(const DataLayout & DL,const AddrMode & AM,Type * Ty,unsigned AS,Instruction * I) const isLegalAddressingMode() argument
2386 translateSetCCForBranch(const SDLoc & DL,SDValue & LHS,SDValue & RHS,ISD::CondCode & CC,SelectionDAG & DAG) translateSetCCForBranch() argument
2733 SDLoc DL(V); convertToScalableVector() local
2745 SDLoc DL(V); convertFromScalableVector() local
2761 getAllOnesMask(MVT VecVT,SDValue VL,const SDLoc & DL,SelectionDAG & DAG) getAllOnesMask() argument
2767 getVLOp(uint64_t NumElts,MVT ContainerVT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getVLOp() argument
2781 getDefaultScalableVLOps(MVT VecVT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getDefaultScalableVLOps() argument
2790 getDefaultVLOps(uint64_t NumElts,MVT ContainerVT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getDefaultVLOps() argument
2803 getDefaultVLOps(MVT VecVT,MVT ContainerVT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getDefaultVLOps() argument
2812 computeVLMax(MVT VecVT,const SDLoc & DL,SelectionDAG & DAG) const computeVLMax() argument
2933 SDLoc DL(Op); lowerFP_TO_INT_SAT() local
2973 SDLoc DL(Op); lowerFP_TO_INT_SAT() local
3044 SDLoc DL(Op); lowerVectorFTRUNC_FCEIL_FFLOOR_FROUND() local
3150 SDLoc DL(Op); lowerVectorStrictFTRUNC_FCEIL_FFLOOR_FROUND() local
3258 SDLoc DL(Op); lowerFTRUNC_FCEIL_FFLOOR_FROUND() local
3282 SDLoc DL(Op); lowerVectorXRINT() local
3303 getVSlidedown(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlidedown() argument
3314 getVSlideup(SelectionDAG & DAG,const RISCVSubtarget & Subtarget,const SDLoc & DL,EVT VT,SDValue Merge,SDValue Op,SDValue Offset,SDValue Mask,SDValue VL,unsigned Policy=RISCVII::TAIL_UNDISTURBED_MASK_UNDISTURBED) getVSlideup() argument
3470 matchSplatAsGather(SDValue SplatVal,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) matchSplatAsGather() argument
3519 SDLoc DL(Op); lowerBuildVectorViaDominantValues() local
3626 SDLoc DL(Op); lowerBuildVectorOfConstants() local
3942 SDLoc DL(Op); lowerBuildVectorViaPacking() local
4025 SDLoc DL(Op); lowerBUILD_VECTOR() local
4237 splatPartsI64WithVL(const SDLoc & DL,MVT VT,SDValue Passthru,SDValue Lo,SDValue Hi,SDValue VL,SelectionDAG & DAG) splatPartsI64WithVL() argument
4293 splatSplitI64WithVL(const SDLoc & DL,MVT VT,SDValue Passthru,SDValue Scalar,SDValue VL,SelectionDAG & DAG) splatSplitI64WithVL() argument
4306 lowerScalarSplat(SDValue Passthru,SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarSplat() argument
4344 lowerScalarInsert(SDValue Scalar,SDValue VL,MVT VT,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerScalarInsert() argument
4558 getDeinterleaveViaVNSRL(const SDLoc & DL,MVT VT,SDValue Src,bool EvenElts,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) getDeinterleaveViaVNSRL() argument
4617 lowerVECTOR_SHUFFLEAsVSlidedown(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlidedown() argument
4694 lowerVECTOR_SHUFFLEAsVSlideup(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlideup() argument
4738 lowerVECTOR_SHUFFLEAsVSlide1(const SDLoc & DL,MVT VT,SDValue V1,SDValue V2,ArrayRef<int> Mask,const RISCVSubtarget & Subtarget,SelectionDAG & DAG) lowerVECTOR_SHUFFLEAsVSlide1() argument
4793 getWideningInterleave(SDValue EvenV,SDValue OddV,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getWideningInterleave() argument
4895 SDLoc DL(SVN); lowerBitreverseShuffle() local
4948 SDLoc DL(SVN); isLegalBitRotate() local
4970 SDLoc DL(SVN); lowerVECTOR_SHUFFLEAsRotate() local
4998 SDLoc DL(SVN); lowerShuffleViaVRegSplitting() local
5081 SDLoc DL(Op); lowerVECTOR_SHUFFLE() local
5407 SDLoc DL(Op); lowerCTLZ_CTTZ_ZERO_UNDEF() local
5520 SDLoc DL(Op); lowerVPCttzElements() local
5570 SDLoc DL(Op); expandUnalignedRVVLoad() local
5600 SDLoc DL(Op); expandUnalignedRVVStore() local
5691 SDLoc DL(Op); lowerSADDSAT_SSUBSAT() local
5713 SDLoc DL(Op); lowerUADDSAT_USUBSAT() local
5728 SDLoc DL(Op); lowerSADDO_SSUBO() local
5745 SDLoc DL(Op); lowerSMULO() local
5759 SDLoc DL(Op); LowerIS_FPCLASS() local
5861 SDLoc DL(Op); lowerFMAXIMUM_FMINIMUM() local
6138 SDLoc DL(Op); SplitVectorOp() local
6164 SDLoc DL(Op); SplitVPOp() local
6193 SDLoc DL(Op); SplitVectorReductionOp() local
6216 SDLoc DL(Op); SplitStrictFPVectorOp() local
6296 SDLoc DL(Op); LowerOperation() local
6384 SDLoc DL(Op); LowerOperation() local
6415 SDLoc DL(Op); LowerOperation() local
6436 SDLoc DL(Op); LowerOperation() local
6473 SDLoc DL(Op); LowerOperation() local
6490 SDLoc DL(Op); LowerOperation() local
6507 SDLoc DL(Op); LowerOperation() local
6537 SDLoc DL(Op); LowerOperation() local
6556 SDLoc DL(Op); LowerOperation() local
6574 SDLoc DL(Op); LowerOperation() local
6708 SDLoc DL(Op); LowerOperation() local
6721 SDLoc DL(Op); LowerOperation() local
6737 SDLoc DL(Op); LowerOperation() local
6751 SDLoc DL(Op); LowerOperation() local
6848 SDLoc DL(Op); LowerOperation() local
6866 SDLoc DL(Op); LowerOperation() local
6937 SDLoc DL(Op); LowerOperation() local
6952 SDLoc DL(Op); LowerOperation() local
7174 SDLoc DL(Op); LowerOperation() local
7193 SDLoc DL(Op); LowerOperation() local
7261 SDLoc DL(Op); LowerOperation() local
7281 getTargetNode(GlobalAddressSDNode * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG,unsigned Flags) getTargetNode() argument
7286 getTargetNode(BlockAddressSDNode * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG,unsigned Flags) getTargetNode() argument
7292 getTargetNode(ConstantPoolSDNode * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG,unsigned Flags) getTargetNode() argument
7298 getTargetNode(JumpTableSDNode * N,const SDLoc & DL,EVT Ty,SelectionDAG & DAG,unsigned Flags) getTargetNode() argument
7306 SDLoc DL(N); getAddr() local
7406 SDLoc DL(N); getStaticTLSAddr() local
7452 SDLoc DL(N); getDynamicTLSAddr() local
7484 SDLoc DL(N); getTLSDescAddr() local
7563 SDLoc DL(N); combineSelectToBinOp() local
7664 SDLoc DL(Sel); foldBinOpIntoSelectIfProfitable() local
7695 SDLoc DL(Op); lowerSELECT() local
7871 SDLoc DL(Op); lowerBRCOND() local
7896 SDLoc DL(Op); lowerVASTART() local
7917 SDLoc DL(Op); lowerFRAMEADDR() local
7943 SDLoc DL(Op); lowerRETURNADDR() local
7962 SDLoc DL(Op); lowerShiftLeftParts() local
8001 SDLoc DL(Op); lowerShiftRightParts() local
8055 SDLoc DL(Op); lowerVectorMaskSplat() local
8081 SDLoc DL(Op); lowerSPLAT_VECTOR_PARTS() local
8111 SDLoc DL(Op); lowerVectorMaskExt() local
8166 SDLoc DL(Op); lowerFixedLengthVectorExtendToRVV() local
8180 SDLoc DL(Op); lowerVectorMaskTruncLike() local
8232 SDLoc DL(Op); lowerVectorTruncLike() local
8294 SDLoc DL(Op); lowerStrictFPExtendOrRoundLike() local
8350 SDLoc DL(Op); lowerVectorFPExtendOrRoundLike() local
8418 getSmallestVTForIndex(MVT VecVT,unsigned MaxIdx,SDLoc DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) getSmallestVTForIndex() argument
8446 SDLoc DL(Op); lowerINSERT_VECTOR_ELT() local
8614 SDLoc DL(Op); lowerEXTRACT_VECTOR_ELT() local
8777 SDLoc DL(Op); lowerVectorIntrinsicScalars() local
8973 SDLoc DL(N); lowerGetVectorLength() local
8996 SDLoc DL(N); lowerCttzElts() local
9018 SDLoc DL(Op); promoteVCIXScalar() local
9080 SDLoc DL(Op); LowerINTRINSIC_WO_CHAIN() local
9357 SDLoc DL(Op); getVCIXISDNodeWCHAIN() local
9408 SDLoc DL(Op); LowerINTRINSIC_W_CHAIN() local
9489 SDLoc DL(Op); LowerINTRINSIC_W_CHAIN() local
9562 SDLoc DL(Op); LowerINTRINSIC_VOID() local
9609 SDLoc DL(Op); LowerINTRINSIC_VOID() local
9712 SDLoc DL(Op); lowerVectorMaskVecReduction() local
9802 lowerReductionSeq(unsigned RVVOpcode,MVT ResVT,SDValue StartValue,SDValue Vec,SDValue Mask,SDValue VL,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) lowerReductionSeq() argument
9832 SDLoc DL(Op); lowerVECREDUCE() local
9885 SDLoc DL(Op); getRVVFPReductionOpAndOperands() local
9918 SDLoc DL(Op); lowerFPVECREDUCE() local
9961 SDLoc DL(Op); lowerVPREDUCE() local
10016 SDLoc DL(Op); lowerINSERT_SUBVECTOR() local
10252 SDLoc DL(Op); lowerEXTRACT_SUBVECTOR() local
10420 widenVectorOpsToi8(SDValue N,const SDLoc & DL,SelectionDAG & DAG) widenVectorOpsToi8() argument
10450 SDLoc DL(Op); lowerVECTOR_DEINTERLEAVE() local
10526 SDLoc DL(Op); lowerVECTOR_INTERLEAVE() local
10617 SDLoc DL(Op); lowerSTEP_VECTOR() local
10647 SDLoc DL(Op); lowerVECTOR_REVERSE() local
10721 SDLoc DL(Op); lowerVECTOR_SPLICE() local
10756 SDLoc DL(Op); lowerFixedLengthVectorLoadToRVV() local
10805 SDLoc DL(Op); lowerFixedLengthVectorStoreToRVV() local
10857 SDLoc DL(Op); lowerMaskedLoad() local
10922 SDLoc DL(Op); lowerMaskedStore() local
10998 SDLoc DL(Op); lowerFixedLengthVectorSetccToRVV() local
11013 SDLoc DL(Op); lowerVectorStrictFSetcc() local
11100 SDLoc DL(Op); lowerABS() local
11138 SDLoc DL(Op); lowerFixedLengthVectorFCOPYSIGNToRVV() local
11172 SDLoc DL(Op); lowerFixedLengthVectorSelectToRVV() local
11207 SDLoc DL(Op); lowerToScalableOp() local
11239 SDLoc DL(Op); lowerVPOp() local
11292 SDLoc DL(Op); lowerVPExtMaskOp() local
11325 SDLoc DL(Op); lowerVPSetCCMaskOp() local
11405 SDLoc DL(Op); lowerVPFPIntConvOp() local
11539 SDLoc DL(Op); lowerVPSpliceExperimental() local
11622 SDLoc DL(Op); lowerVPSplatExperimental() local
11646 SDLoc DL(Op); lowerVPReverseExperimental() local
11783 SDLoc DL(Op); lowerLogicVPOp() local
11792 SDLoc DL(Op); lowerVPStridedLoad() local
11838 SDLoc DL(Op); lowerVPStridedStore() local
11881 SDLoc DL(Op); lowerMaskedGather() local
11980 SDLoc DL(Op); lowerMaskedScatter() local
12061 SDLoc DL(Op); lowerGET_ROUNDING() local
12092 SDLoc DL(Op); lowerSET_ROUNDING() local
12164 SDLoc DL(N); customLegalizeToWOp() local
12176 SDLoc DL(N); customLegalizeToWOpWithSExt() local
12188 SDLoc DL(N); ReplaceNodeResults() local
12397 SDLoc DL(N); ReplaceNodeResults() local
12958 const SDLoc DL(N); combineBinOpOfExtractToReduceTree() local
13124 SDLoc DL(N); combineBinOpToReduce() local
13181 SDLoc DL(N); transformAddShlImm() local
13337 SDLoc DL(N); transformAddImmMulImm() local
13402 SDLoc DL(N); combineAddOfBooleanXor() local
13450 SDLoc DL(N); combineSubOfBoolean() local
13528 SDLoc DL(N); performSUBCombine() local
13586 SDLoc DL(N); combineDeMorganOfBoolean() local
13653 SDLoc DL(N); combineTruncSelectToSMaxUSat() local
13675 SDLoc DL(N0); performTRUNCATECombine() local
13703 SDLoc DL(N); performANDCombine() local
13752 SDLoc DL(N); combineOrOfCZERO() local
13801 SDLoc DL(N); performXORCombine() local
13815 SDLoc DL(N); performXORCombine() local
13826 SDLoc DL(N0); performXORCombine() local
13840 SDLoc DL(N); performXORCombine() local
13899 SDLoc DL(N); expandMul() local
13922 SDLoc DL(N); expandMul() local
13939 SDLoc DL(N); expandMul() local
13958 SDLoc DL(N); expandMul() local
13972 SDLoc DL(N); expandMul() local
13984 SDLoc DL(N); expandMul() local
14000 SDLoc DL(N); expandMul() local
14044 SDLoc DL(N); combineVectorMulToSraBitcast() local
14058 SDLoc DL(N); performMULCombine() local
14110 SDLoc DL(N); narrowIndex() local
14333 SDLoc DL(OrigOperand); getOrCreateExtendedOp() local
14693 SDLoc DL(Root); getMaskAndVL() local
15307 SDLoc DL(N); performFP_TO_INTCombine() local
15430 SDLoc DL(N); performFP_TO_INT_SATCombine() local
15460 SDLoc DL(N); performBITREVERSECombine() local
15630 SDLoc DL(N); performSRACombine() local
15685 SDLoc DL(N); performSRACombine() local
15772 combine_CC(SDValue & LHS,SDValue & RHS,SDValue & CC,const SDLoc & DL,SelectionDAG & DAG,const RISCVSubtarget & Subtarget) combine_CC() argument
15897 SDLoc DL(N); tryFoldSelectIntoOp() local
15979 SDLoc DL(N); useInversedSetcc() local
16031 SDLoc DL(N); performBUILD_VECTORCombine() local
16092 SDLoc DL(N); performINSERT_VECTOR_ELTCombine() local
16161 SDLoc DL(N); performCONCAT_VECTORSCombine() local
16325 SDLoc DL(N); combineToVWMACC() local
16348 SDLoc DL(N); combineToVWMACC() local
16355 legalizeScatterGatherIndexType(SDLoc DL,SDValue & Index,ISD::MemIndexType & IndexType,RISCVTargetLowering::DAGCombinerInfo & DCI) legalizeScatterGatherIndexType() argument
16566 SDLoc DL(N); combineTruncToVnclip() local
16658 SDLoc DL(N); PerformDAGCombine() local
16753 SDLoc DL(N); PerformDAGCombine() local
16793 SDLoc DL(N); PerformDAGCombine() local
16920 SDLoc DL(N); PerformDAGCombine() local
17019 SDLoc DL(N); PerformDAGCombine() local
17054 SDLoc DL(N); PerformDAGCombine() local
17068 SDLoc DL(N); PerformDAGCombine() local
17168 SDLoc DL(N); PerformDAGCombine() local
17204 SDLoc DL(N); PerformDAGCombine() local
17229 SDLoc DL(N); PerformDAGCombine() local
17254 SDLoc DL(N); PerformDAGCombine() local
17277 SDLoc DL(N); PerformDAGCombine() local
17330 SDLoc DL(N); PerformDAGCombine() local
17407 SDLoc DL(N); PerformDAGCombine() local
17597 SDLoc DL(N); PerformDAGCombine() local
17618 SDLoc DL(N); PerformDAGCombine() local
17736 SDLoc DL(Op); targetShrinkDemandedConstant() local
18135 DebugLoc DL = MI.getDebugLoc(); emitReadCounterWidePseudo() local
18167 DebugLoc DL = MI.getDebugLoc(); emitSplitF64Pseudo() local
18203 DebugLoc DL = MI.getDebugLoc(); emitBuildPairF64Pseudo() local
18253 DebugLoc DL = MI.getDebugLoc(); emitQuietFCMP() local
18326 const DebugLoc &DL = First.getDebugLoc(); EmitLoweredCascadedSelect() local
18470 DebugLoc DL = MI.getDebugLoc(); emitSelectPseudo() local
18554 DebugLoc DL = MI.getDebugLoc(); emitVFROUND_NOEXCEPT_MASK() local
18674 DebugLoc DL = MI.getDebugLoc(); emitFROUND() local
18991 CC_RISCV(const DataLayout & DL,RISCVABI::ABI ABI,unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State,bool IsFixed,bool IsRet,Type * OrigTy,const RISCVTargetLowering & TLI,RVVArgDispatcher & RVVDispatcher) CC_RISCV() argument
19314 convertLocVTToValVT(SelectionDAG & DAG,SDValue Val,const CCValAssign & VA,const SDLoc & DL,const RISCVSubtarget & Subtarget) convertLocVTToValVT() argument
19345 unpackFromRegLoc(SelectionDAG & DAG,SDValue Chain,const CCValAssign & VA,const SDLoc & DL,const ISD::InputArg & In,const RISCVTargetLowering & TLI) unpackFromRegLoc() argument
19378 convertValVTToLocVT(SelectionDAG & DAG,SDValue Val,const CCValAssign & VA,const SDLoc & DL,const RISCVSubtarget & Subtarget) convertValVTToLocVT() argument
19411 unpackFromMemLoc(SelectionDAG & DAG,SDValue Chain,const CCValAssign & VA,const SDLoc & DL) unpackFromMemLoc() argument
19447 unpackF64OnRV32DSoftABI(SelectionDAG & DAG,SDValue Chain,const CCValAssign & VA,const CCValAssign & HiVA,const SDLoc & DL) unpackF64OnRV32DSoftABI() argument
19478 CC_RISCV_FastCC(const DataLayout & DL,RISCVABI::ABI ABI,unsigned ValNo,MVT ValVT,MVT LocVT,CCValAssign::LocInfo LocInfo,ISD::ArgFlagsTy ArgFlags,CCState & State,bool IsFixed,bool IsRet,Type * OrigTy,const RISCVTargetLowering & TLI,RVVArgDispatcher & RVVDispatcher) CC_RISCV_FastCC() argument
19659 LowerFormalArguments(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::InputArg> & Ins,const SDLoc & DL,SelectionDAG & DAG,SmallVectorImpl<SDValue> & InVals) const LowerFormalArguments() argument
19893 SDLoc &DL = CLI.DL; LowerCall() local
20216 LowerReturn(SDValue Chain,CallingConv::ID CallConv,bool IsVarArg,const SmallVectorImpl<ISD::OutputArg> & Outs,const SmallVectorImpl<SDValue> & OutVals,const SDLoc & DL,SelectionDAG & DAG) const LowerReturn() argument
21075 const DataLayout &DL = AI->getDataLayout(); emitMaskedAtomicRMWIntrinsic() local
21476 splitValueIntoRegisterParts(SelectionDAG & DAG,const SDLoc & DL,SDValue Val,SDValue * Parts,unsigned NumParts,MVT PartVT,std::optional<CallingConv::ID> CC) const splitValueIntoRegisterParts() argument
21531 joinRegisterPartsIntoValue(SelectionDAG & DAG,const SDLoc & DL,const SDValue * Parts,unsigned NumParts,MVT PartVT,EVT ValueVT,std::optional<CallingConv::ID> CC) const joinRegisterPartsIntoValue() argument
22099 const DataLayout &DL = MF->getDataLayout(); constructArgInfos() local
[all...] |
| H A D | RISCVISelDAGToDAG.cpp | 66 SDLoc DL(N); in PreprocessISelDAG() local
70 Src = CurDAG->getNode(ISD::ANY_EXTEND, DL, Subtarget->getXLenVT(), in PreprocessISelDAG()
72 Result = CurDAG->getNode(Opc, DL, VT, CurDAG->getUNDEF(VT), Src, VL); in PreprocessISelDAG()
89 SDLoc DL(N); in PreprocessISelDAG() local
98 Lo = CurDAG->getStore(Chain, DL, Lo, StackSlot, MPI, Align(8)); in PreprocessISelDAG()
101 CurDAG->getMemBasePlusOffset(StackSlot, TypeSize::getFixed(4), DL); in PreprocessISelDAG()
102 Hi = CurDAG->getStore(Chain, DL, Hi, OffsetSlot, MPI.getWithOffset(4), in PreprocessISelDAG()
105 Chain = CurDAG->getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi); in PreprocessISelDAG()
109 CurDAG->getTargetConstant(Intrinsic::riscv_vlse, DL, MVT::i64); in PreprocessISelDAG()
117 Result = CurDAG->getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, in PreprocessISelDAG()
[all …]
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| H A D | RISCVExpandAtomicPseudoInsts.cpp | 260 DebugLoc DL, MachineBasicBlock *ThisMBB, in doAtomicBinOpExpansion()
277 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)), DestReg) in insertMaskedMerge()
283 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg) in insertMaskedMerge()
286 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg) in insertMaskedMerge()
291 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)), ScratchReg) in insertMaskedMerge()
294 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in insertMaskedMerge()
300 static void insertMaskedMerge(const RISCVInstrInfo *TII, DebugLoc DL, in doMaskedAtomicBinOpExpansion()
311 BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg) in doMaskedAtomicBinOpExpansion()
314 BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg) in doMaskedAtomicBinOpExpansion()
317 BuildMI(MBB, DL, TI in doMaskedAtomicBinOpExpansion()
236 doAtomicBinOpExpansion(const RISCVInstrInfo * TII,MachineInstr & MI,DebugLoc DL,MachineBasicBlock * ThisMBB,MachineBasicBlock * LoopMBB,MachineBasicBlock * DoneMBB,AtomicRMWInst::BinOp BinOp,int Width) doAtomicBinOpExpansion() argument
275 insertMaskedMerge(const RISCVInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register DestReg,Register OldValReg,Register NewValReg,Register MaskReg,Register ScratchReg) insertMaskedMerge() argument
298 doMaskedAtomicBinOpExpansion(const RISCVInstrInfo * TII,MachineInstr & MI,DebugLoc DL,MachineBasicBlock * ThisMBB,MachineBasicBlock * LoopMBB,MachineBasicBlock * DoneMBB,AtomicRMWInst::BinOp BinOp,int Width) doMaskedAtomicBinOpExpansion() argument
365 DebugLoc DL = MI.getDebugLoc(); expandAtomicBinOp() local
398 insertSext(const RISCVInstrInfo * TII,DebugLoc DL,MachineBasicBlock * MBB,Register ValReg,Register ShamtReg) insertSext() argument
418 DebugLoc DL = MI.getDebugLoc(); expandAtomicMinMaxOp() local
600 DebugLoc DL = MI.getDebugLoc(); expandAtomicCmpXchg() local
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 587 SDLoc DL(N); in performDivRemCombine() local
589 SDValue DivRem = DAG.getNode(Opc, DL, MVT::Glue, in performDivRemCombine()
596 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, DL, LO, Ty, in performDivRemCombine()
605 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, DL, in performDivRemCombine()
664 SDLoc DL(Op); in createFPCmp() local
670 return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, in createFPCmp()
671 DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); in createFPCmp()
676 SDValue False, const SDLoc &DL) { in createCMovFP() argument
681 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, in createCMovFP()
715 const SDLoc DL(N); in performSELECTCombine() local
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| H A D | MipsSEISelLowering.cpp | 411 SDLoc DL(Op); in lowerSELECT() local
416 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
417 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), in lowerSELECT()
792 static SDValue genConstMult(SDValue X, APInt C, const SDLoc &DL, EVT VT, in genConstMult() argument
796 return DAG.getConstant(0, DL, VT); in genConstMult()
804 return DAG.getNode(ISD::SHL, DL, VT, X, in genConstMult()
805 DAG.getConstant(C.logBase2(), DL, ShiftTy)); in genConstMult()
816 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); in genConstMult()
817 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); in genConstMult()
818 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1); in genConstMult()
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| H A D | MipsSEISelDAGToDAG.cpp | 206 void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const { in selectAddE()
234 SDValue CstOne = CurDAG->getTargetConstant(1, DL, MVT::i32); in selectAddE()
236 SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32); in selectAddE()
238 SDNode *DSPCtrlField = CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32, in selectAddE()
242 Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne); in selectAddE()
245 CurDAG->getTargetConstant(6, DL, MVT::i32), CstOne, in selectAddE()
247 SDNode *DSPCFWithCarry = CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, Ops); in selectAddE()
258 CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps); in selectAddE()
260 SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue, in selectAddE()
747 SDLoc DL(Node); in trySelect() local
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 215 EVT M68kTargetLowering::getSetCCResultType(const DataLayout &DL, in getSetCCResultType() argument
221 MVT M68kTargetLowering::getScalarShiftAmountTy(const DataLayout &DL, in getScalarShiftAmountTy() argument
226 return MVT::getIntegerVT(DL.getPointerSizeInBits(0)); in getScalarShiftAmountTy()
265 SelectionDAG &DAG, const SDLoc &DL) { in CreateCopyOfByValArgument() argument
266 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32); in CreateCopyOfByValArgument()
269 Chain, DL, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(), in CreateCopyOfByValArgument()
402 const SDLoc &DL) const { in EmitTailCallLoadRetAddr()
407 OutRetAddr = DAG.getLoad(VT, DL, Chain, OutRetAddr, MachinePointerInfo()); in EmitTailCallLoadRetAddr()
413 EVT PtrVT, unsigned SlotSize, int FPDiff, const SDLoc &DL) const { in EmitTailCallStoreRetAddr()
424 Chain, DL, RetFI, NewFI, in EmitTailCallStoreRetAddr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430FrameLowering.cpp | 47 const DebugLoc &DL, in BuildCFI() argument
52 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in BuildCFI()
59 const DebugLoc &DL, bool IsPrologue) const { in emitCalleeSavedFrameMoves() argument
74 BuildCFI(MBB, MBBI, DL, in emitCalleeSavedFrameMoves()
77 BuildCFI(MBB, MBBI, DL, in emitCalleeSavedFrameMoves()
92 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); in emitPrologue() local
110 BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) in emitPrologue()
116 BuildCFI(MBB, MBBI, DL, in emitPrologue()
123 MBB, MBBI, DL, in emitPrologue()
128 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::R4) in emitPrologue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelDAGToDAG.cpp | 82 bool fillGenericConstant(const DataLayout &DL, const Constant *CV,
84 bool fillConstantDataArray(const DataLayout &DL, const ConstantDataArray *CDA,
86 bool fillConstantArray(const DataLayout &DL, const ConstantArray *CA,
88 bool fillConstantStruct(const DataLayout &DL, const ConstantStruct *CS,
111 SDLoc DL(Addr); in INITIALIZE_PASS() local
114 Offset = CurDAG->getTargetConstant(0, DL, MVT::i64); in INITIALIZE_PASS()
132 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64); in INITIALIZE_PASS()
138 Offset = CurDAG->getTargetConstant(0, DL, MVT::i64); in INITIALIZE_PASS()
145 SDLoc DL(Addr); in SelectFIAddr() local
159 Offset = CurDAG->getTargetConstant(CN->getSExtValue(), DL, MVT::i64); in SelectFIAddr()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Mangler.cpp | 37 const DataLayout &DL, char Prefix) { in getNameWithPrefixImpl() argument
49 if (DL.doNotMangleLeadingQuestionMark() && Name[0] == '?') in getNameWithPrefixImpl()
53 OS << DL.getPrivateGlobalPrefix(); in getNameWithPrefixImpl()
55 OS << DL.getLinkerPrivateGlobalPrefix(); in getNameWithPrefixImpl()
65 const DataLayout &DL, in getNameWithPrefixImpl() argument
67 char Prefix = DL.getGlobalPrefix(); in getNameWithPrefixImpl()
68 return getNameWithPrefixImpl(OS, GVName, PrefixTy, DL, Prefix); in getNameWithPrefixImpl()
72 const DataLayout &DL) { in getNameWithPrefix() argument
73 return getNameWithPrefixImpl(OS, GVName, DL, Default); in getNameWithPrefix()
77 const Twine &GVName, const DataLayout &DL) { in getNameWithPrefix() argument
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 231 const DebugLoc &DL, int64_t NumBytes, in emitSPUpdate() argument
251 BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING)).addImm(Offset); in emitSPUpdate()
267 BuildMI(MBB, MBBI, DL, TII.get(getMOVriOpcode(Is64Bit, Offset)), Reg) in emitSPUpdate()
270 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr) in emitSPUpdate()
284 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r)) in emitSPUpdate()
293 BuildMI(MBB, MBBI, DL, TII.get(getMOVriOpcode(Is64Bit, Offset)), Rax) in emitSPUpdate()
296 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax) in emitSPUpdate()
302 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax), in emitSPUpdate()
305 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr), in emitSPUpdate()
321 BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 396 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments() argument
401 return LowerCCCArguments(Chain, CallConv, IsVarArg, Ins, DL, DAG, InVals); in LowerFormalArguments()
410 SDLoc &DL = CLI.DL; in LowerCall() local
427 OutVals, Ins, DL, DAG, InVals); in LowerCall()
437 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerCCCArguments() argument
462 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, RegVT); in LowerCCCArguments()
468 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerCCCArguments()
471 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerCCCArguments()
475 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerCCCArguments()
502 VA.getLocVT(), DL, Chain, FIN, in LowerCCCArguments()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | ConstantFolding.h | 48 const DataLayout &DL,
56 Constant *ConstantFoldInstruction(Instruction *I, const DataLayout &DL,
62 Constant *ConstantFoldConstant(const Constant *C, const DataLayout &DL,
78 const DataLayout &DL,
87 unsigned Predicate, Constant *LHS, Constant *RHS, const DataLayout &DL,
93 const DataLayout &DL);
98 Constant *RHS, const DataLayout &DL);
104 Constant *RHS, const DataLayout &DL,
128 const DataLayout &DL);
133 const DataLayout &DL);
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64PointerAuth.cpp | 79 MachineBasicBlock::iterator MBBI, DebugLoc DL, in BuildPACM() argument
87 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ADR)) in BuildPACM()
95 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACM)).setMIFlag(Flags); in BuildPACM()
109 DebugLoc DL; in signLR() local
112 BuildMI(MBB, MBBI, DL, TII->get(AArch64::EMITBKEY)) in signLR()
126 BuildMI(MBB, MBBI, DL, in signLR()
132 BuildPACM(*Subtarget, MBB, MBBI, DL, MachineInstr::FrameSetup); in signLR()
133 BuildMI(MBB, MBBI, DL, in signLR()
155 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) in signLR()
159 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PACSignLR)) in signLR()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 377 MVT WebAssemblyTargetLowering::getPointerTy(const DataLayout &DL, in getPointerTy() argument
383 return TargetLowering::getPointerTy(DL, AS); in getPointerTy()
386 MVT WebAssemblyTargetLowering::getPointerMemTy(const DataLayout &DL, in getPointerMemTy() argument
392 return TargetLowering::getPointerMemTy(DL, AS); in getPointerMemTy()
460 static MachineBasicBlock *LowerFPToInt(MachineInstr &MI, DebugLoc DL, in LowerFPToInt() argument
517 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg); in LowerFPToInt()
519 BuildMI(BB, DL, TII.get(FConst), Tmp1) in LowerFPToInt()
521 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
529 BuildMI(BB, DL, TII.get(FConst), Tmp1) in LowerFPToInt()
531 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1); in LowerFPToInt()
[all …]
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