Lines Matching refs:DL
430 SDLoc DL(Op); in LowerOperation() local
436 DAG.getConstant(0, DL, MVT::i32), // SWZ_X in LowerOperation()
437 DAG.getConstant(1, DL, MVT::i32), // SWZ_Y in LowerOperation()
438 DAG.getConstant(2, DL, MVT::i32), // SWZ_Z in LowerOperation()
439 DAG.getConstant(3, DL, MVT::i32) // SWZ_W in LowerOperation()
441 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, Op.getValueType(), Args); in LowerOperation()
453 SDLoc DL(Op); in LowerOperation() local
470 DAG.getConstant(TextureOp, DL, MVT::i32), in LowerOperation()
472 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
473 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
474 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
475 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
479 DAG.getConstant(0, DL, MVT::i32), in LowerOperation()
480 DAG.getConstant(1, DL, MVT::i32), in LowerOperation()
481 DAG.getConstant(2, DL, MVT::i32), in LowerOperation()
482 DAG.getConstant(3, DL, MVT::i32), in LowerOperation()
490 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs); in LowerOperation()
494 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
495 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
496 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
497 DAG.getConstant(0, DL, MVT::i32)), in LowerOperation()
498 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
499 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
500 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
501 DAG.getConstant(1, DL, MVT::i32)), in LowerOperation()
502 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
503 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
504 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
505 DAG.getConstant(2, DL, MVT::i32)), in LowerOperation()
506 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(1), in LowerOperation()
507 DAG.getConstant(3, DL, MVT::i32)), in LowerOperation()
508 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, Op.getOperand(2), in LowerOperation()
509 DAG.getConstant(3, DL, MVT::i32)) in LowerOperation()
511 return DAG.getNode(AMDGPUISD::DOT4, DL, MVT::f32, Args); in LowerOperation()
517 return DAG.getConstant(ByteOffset, DL, PtrVT); in LowerOperation()
520 return LowerImplicitParameter(DAG, VT, DL, 0); in LowerOperation()
522 return LowerImplicitParameter(DAG, VT, DL, 1); in LowerOperation()
524 return LowerImplicitParameter(DAG, VT, DL, 2); in LowerOperation()
526 return LowerImplicitParameter(DAG, VT, DL, 3); in LowerOperation()
528 return LowerImplicitParameter(DAG, VT, DL, 4); in LowerOperation()
530 return LowerImplicitParameter(DAG, VT, DL, 5); in LowerOperation()
532 return LowerImplicitParameter(DAG, VT, DL, 6); in LowerOperation()
534 return LowerImplicitParameter(DAG, VT, DL, 7); in LowerOperation()
536 return LowerImplicitParameter(DAG, VT, DL, 8); in LowerOperation()
564 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1)); in LowerOperation()
567 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1)); in LowerOperation()
623 SDLoc DL(Vector); in vectorToVerticalVector() local
629 Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Vector, in vectorToVerticalVector()
630 DAG.getVectorIdxConstant(i, DL))); in vectorToVerticalVector()
633 return DAG.getNode(AMDGPUISD::BUILD_VERTICAL_VECTOR, DL, VecVT, Args); in vectorToVerticalVector()
638 SDLoc DL(Op); in LowerEXTRACT_VECTOR_ELT() local
647 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, Op.getValueType(), in LowerEXTRACT_VECTOR_ELT()
653 SDLoc DL(Op); in LowerINSERT_VECTOR_ELT() local
663 SDValue Insert = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, Op.getValueType(), in LowerINSERT_VECTOR_ELT()
675 const DataLayout &DL = DAG.getDataLayout(); in LowerGlobalAddress() local
677 MVT ConstPtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS); in LowerGlobalAddress()
688 SDLoc DL(Op); in LowerTrig() local
691 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT, in LowerTrig()
692 DAG.getNode(ISD::FADD, DL, VT, in LowerTrig()
693 DAG.getNode(ISD::FMUL, DL, VT, Arg, in LowerTrig()
694 DAG.getConstantFP(0.15915494309, DL, MVT::f32)), in LowerTrig()
695 DAG.getConstantFP(0.5, DL, MVT::f32))); in LowerTrig()
707 SDValue TrigVal = DAG.getNode(TrigNode, DL, VT, in LowerTrig()
708 DAG.getNode(ISD::FADD, DL, VT, FractPart, in LowerTrig()
709 DAG.getConstantFP(-0.5, DL, MVT::f32))); in LowerTrig()
713 return DAG.getNode(ISD::FMUL, DL, VT, TrigVal, in LowerTrig()
714 DAG.getConstantFP(numbers::pif, DL, MVT::f32)); in LowerTrig()
726 SDLoc DL(Op); in LowerUADDSUBO() local
732 SDValue OVF = DAG.getNode(ovf, DL, VT, Lo, Hi); in LowerUADDSUBO()
734 OVF = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, OVF, in LowerUADDSUBO()
737 SDValue Res = DAG.getNode(mainop, DL, VT, Lo, Hi); in LowerUADDSUBO()
739 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
743 SDLoc DL(Op); in lowerFP_TO_UINT() local
746 DL, in lowerFP_TO_UINT()
748 Op, DAG.getConstantFP(1.0f, DL, MVT::f32), in lowerFP_TO_UINT()
753 SDLoc DL(Op); in lowerFP_TO_SINT() local
756 DL, in lowerFP_TO_SINT()
758 Op, DAG.getConstantFP(-1.0f, DL, MVT::f32), in lowerFP_TO_SINT()
763 const SDLoc &DL, in LowerImplicitParameter() argument
772 return DAG.getLoad(VT, DL, DAG.getEntryNode(), in LowerImplicitParameter()
773 DAG.getConstant(ByteOffset, DL, MVT::i32), // PTR in LowerImplicitParameter()
800 SDLoc DL(Op); in LowerSELECT_CC() local
812 SDValue MinMax = combineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI); in LowerSELECT_CC()
851 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC); in LowerSELECT_CC()
892 True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True); in LowerSELECT_CC()
893 False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False); in LowerSELECT_CC()
908 SDValue SelectNode = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, in LowerSELECT_CC()
912 return DAG.getNode(ISD::BITCAST, DL, VT, SelectNode); in LowerSELECT_CC()
920 HWTrue = DAG.getConstantFP(1.0f, DL, CompareVT); in LowerSELECT_CC()
921 HWFalse = DAG.getConstantFP(0.0f, DL, CompareVT); in LowerSELECT_CC()
923 HWTrue = DAG.getConstant(-1, DL, CompareVT); in LowerSELECT_CC()
924 HWFalse = DAG.getConstant(0, DL, CompareVT); in LowerSELECT_CC()
932 SDValue Cond = DAG.getNode(ISD::SELECT_CC, DL, CompareVT, LHS, RHS, HWTrue, HWFalse, CC); in LowerSELECT_CC()
934 return DAG.getNode(ISD::SELECT_CC, DL, VT, in LowerSELECT_CC()
980 SDLoc DL(Ptr); in stackPtrToRegIndex() local
981 return DAG.getNode(ISD::SRL, DL, Ptr.getValueType(), Ptr, in stackPtrToRegIndex()
982 DAG.getConstant(SRLPad, DL, MVT::i32)); in stackPtrToRegIndex()
1016 SDLoc DL(Store); in lowerPrivateTruncStore() local
1025 Mask = DAG.getConstant(0xff, DL, MVT::i32); in lowerPrivateTruncStore()
1028 Mask = DAG.getConstant(0xffff, DL, MVT::i32); in lowerPrivateTruncStore()
1043 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateTruncStore()
1048 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1049 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateTruncStore()
1054 SDValue Dst = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateTruncStore()
1059 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateTruncStore()
1060 DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateTruncStore()
1063 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateTruncStore()
1064 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateTruncStore()
1068 SDValue SExtValue = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i32, in lowerPrivateTruncStore()
1072 SDValue MaskedValue = DAG.getZeroExtendInReg(SExtValue, DL, MemVT); in lowerPrivateTruncStore()
1075 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, MVT::i32, in lowerPrivateTruncStore()
1079 SDValue DstMask = DAG.getNode(ISD::SHL, DL, MVT::i32, Mask, ShiftAmt); in lowerPrivateTruncStore()
1083 DstMask = DAG.getNOT(DL, DstMask, MVT::i32); in lowerPrivateTruncStore()
1086 Dst = DAG.getNode(ISD::AND, DL, MVT::i32, Dst, DstMask); in lowerPrivateTruncStore()
1089 SDValue Value = DAG.getNode(ISD::OR, DL, MVT::i32, Dst, ShiftedValue); in lowerPrivateTruncStore()
1093 SDValue NewStore = DAG.getStore(Chain, DL, Value, Ptr, PtrInfo); in lowerPrivateTruncStore()
1098 Chain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, NewStore); in lowerPrivateTruncStore()
1116 SDLoc DL(Op); in LowerSTORE() local
1126 SDValue NewChain = DAG.getNode(AMDGPUISD::DUMMY_CHAIN, DL, MVT::Other, Chain); in LowerSTORE()
1129 NewChain, DL, Value, Ptr, StoreNode->getPointerInfo(), MemVT, in LowerSTORE()
1146 SDValue DWordAddr = DAG.getNode(ISD::SRL, DL, PtrVT, Ptr, in LowerSTORE()
1147 DAG.getConstant(2, DL, PtrVT)); in LowerSTORE()
1156 MaskConstant = DAG.getConstant(0xFF, DL, MVT::i32); in LowerSTORE()
1160 MaskConstant = DAG.getConstant(0xFFFF, DL, MVT::i32); in LowerSTORE()
1163 SDValue ByteIndex = DAG.getNode(ISD::AND, DL, PtrVT, Ptr, in LowerSTORE()
1164 DAG.getConstant(0x00000003, DL, PtrVT)); in LowerSTORE()
1165 SDValue BitShift = DAG.getNode(ISD::SHL, DL, VT, ByteIndex, in LowerSTORE()
1166 DAG.getConstant(3, DL, VT)); in LowerSTORE()
1169 SDValue Mask = DAG.getNode(ISD::SHL, DL, VT, MaskConstant, BitShift); in LowerSTORE()
1172 SDValue TruncValue = DAG.getNode(ISD::AND, DL, VT, Value, MaskConstant); in LowerSTORE()
1173 SDValue ShiftedValue = DAG.getNode(ISD::SHL, DL, VT, TruncValue, BitShift); in LowerSTORE()
1179 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1180 DAG.getConstant(0, DL, MVT::i32), in LowerSTORE()
1183 SDValue Input = DAG.getBuildVector(MVT::v4i32, DL, Src); in LowerSTORE()
1185 return DAG.getMemIntrinsicNode(AMDGPUISD::STORE_MSKOR, DL, in LowerSTORE()
1191 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr); in LowerSTORE()
1196 Chain = DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand()); in LowerSTORE()
1212 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, PtrVT, DWordAddr); in LowerSTORE()
1213 return DAG.getStore(Chain, DL, Value, Ptr, StoreNode->getMemOperand()); in LowerSTORE()
1263 SDLoc DL(Op); in lowerPrivateExtLoad() local
1275 LoadPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr, Offset); in lowerPrivateExtLoad()
1280 SDValue Ptr = DAG.getNode(ISD::AND, DL, MVT::i32, LoadPtr, in lowerPrivateExtLoad()
1281 DAG.getConstant(0xfffffffc, DL, MVT::i32)); in lowerPrivateExtLoad()
1286 SDValue Read = DAG.getLoad(MVT::i32, DL, Chain, Ptr, PtrInfo); in lowerPrivateExtLoad()
1289 SDValue ByteIdx = DAG.getNode(ISD::AND, DL, MVT::i32, in lowerPrivateExtLoad()
1290 LoadPtr, DAG.getConstant(0x3, DL, MVT::i32)); in lowerPrivateExtLoad()
1293 SDValue ShiftAmt = DAG.getNode(ISD::SHL, DL, MVT::i32, ByteIdx, in lowerPrivateExtLoad()
1294 DAG.getConstant(3, DL, MVT::i32)); in lowerPrivateExtLoad()
1297 SDValue Ret = DAG.getNode(ISD::SRL, DL, MVT::i32, Read, ShiftAmt); in lowerPrivateExtLoad()
1304 Ret = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, MVT::i32, Ret, MemEltVTNode); in lowerPrivateExtLoad()
1306 Ret = DAG.getZeroExtendInReg(Ret, DL, MemEltVT); in lowerPrivateExtLoad()
1314 return DAG.getMergeValues(Ops, DL); in lowerPrivateExtLoad()
1328 SDLoc DL(Op); in LowerLOAD() local
1338 return DAG.getMergeValues(Ops, DL); in LowerLOAD()
1353 Result = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::v4i32, in LowerLOAD()
1354 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, in LowerLOAD()
1355 DAG.getConstant(4, DL, MVT::i32)), in LowerLOAD()
1358 DL, MVT::i32)); in LowerLOAD()
1361 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in LowerLOAD()
1362 DAG.getConstant(0, DL, MVT::i32)); in LowerLOAD()
1369 return DAG.getMergeValues(MergedValues, DL); in LowerLOAD()
1382 ISD::EXTLOAD, DL, VT, Chain, Ptr, LoadNode->getPointerInfo(), MemVT, in LowerLOAD()
1384 SDValue Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT, NewLoad, in LowerLOAD()
1388 return DAG.getMergeValues(MergedValues, DL); in LowerLOAD()
1398 Ptr = DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(2, DL, MVT::i32)); in LowerLOAD()
1399 Ptr = DAG.getNode(AMDGPUISD::DWORDADDR, DL, MVT::i32, Ptr); in LowerLOAD()
1400 return DAG.getLoad(MVT::i32, DL, Chain, Ptr, LoadNode->getMemOperand()); in LowerLOAD()
1456 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments() argument
1482 SDValue Register = DAG.getCopyFromReg(Chain, DL, Reg, VT); in LowerFormalArguments()
1512 ISD::UNINDEXED, Ext, VT, DL, Chain, in LowerFormalArguments()
1513 DAG.getConstant(PartOffset, DL, MVT::i32), DAG.getUNDEF(MVT::i32), in LowerFormalArguments()
1524 EVT R600TargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &, in getSetCCResultType() argument
1564 SDLoc DL(VectorEntry); in CompactSwizzlableVector() local
1569 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in CompactSwizzlableVector()
1570 DAG.getIntPtrConstant(i, DL)); in CompactSwizzlableVector()
1608 SDLoc DL(VectorEntry); in ReorganizeVector() local
1614 NewBldVec[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltTy, VectorEntry, in ReorganizeVector()
1615 DAG.getIntPtrConstant(i, DL)); in ReorganizeVector()
1644 const SDLoc &DL) const { in OptimizeSwizzle()
1652 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1660 Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32); in OptimizeSwizzle()
1668 SDLoc DL(LoadNode); in constBufferLoad() local
1690 SDValue NewPtr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr, in constBufferLoad()
1691 DAG.getConstant(4 * i + ConstantBlock * 16, DL, MVT::i32)); in constBufferLoad()
1692 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr); in constBufferLoad()
1700 SDValue Result = DAG.getBuildVector(NewVT, DL, ArrayRef(Slots, NumElements)); in constBufferLoad()
1702 Result = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, Result, in constBufferLoad()
1703 DAG.getConstant(0, DL, MVT::i32)); in constBufferLoad()
1709 return DAG.getMergeValues(MergedValues, DL); in constBufferLoad()
1719 SDLoc DL(N); in PerformDAGCombine() local
1726 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0), in PerformDAGCombine()
1751 return DAG.getNode(ISD::SELECT_CC, DL, N->getValueType(0), in PerformDAGCombine()
1754 DAG.getConstant(-1, DL, MVT::i32), // True in PerformDAGCombine()
1755 DAG.getConstant(0, DL, MVT::i32), // False in PerformDAGCombine()
1802 DAG.getNode(ISD::ANY_EXTEND, DL, OpVT, InVal) : in PerformDAGCombine()
1803 DAG.getNode(ISD::TRUNCATE, DL, OpVT, InVal); in PerformDAGCombine()
1808 return DAG.getBuildVector(VT, DL, Ops); in PerformDAGCombine()
1827 return DAG.getNode(ISD::BITCAST, DL, N->getVTList(), in PerformDAGCombine()
1868 return DAG.getSelectCC(DL, in PerformDAGCombine()
1895 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[4], DAG, DL); in PerformDAGCombine()
1896 return DAG.getNode(AMDGPUISD::R600_EXPORT, DL, N->getVTList(), NewArgs); in PerformDAGCombine()
1924 NewArgs[1] = OptimizeSwizzle(N->getOperand(1), &NewArgs[2], DAG, DL); in PerformDAGCombine()
1925 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, N->getVTList(), NewArgs); in PerformDAGCombine()