Lines Matching refs:DL
215 EVT M68kTargetLowering::getSetCCResultType(const DataLayout &DL, in getSetCCResultType() argument
221 MVT M68kTargetLowering::getScalarShiftAmountTy(const DataLayout &DL, in getScalarShiftAmountTy() argument
226 return MVT::getIntegerVT(DL.getPointerSizeInBits(0)); in getScalarShiftAmountTy()
265 SelectionDAG &DAG, const SDLoc &DL) { in CreateCopyOfByValArgument() argument
266 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32); in CreateCopyOfByValArgument()
269 Chain, DL, Dst, Src, SizeNode, Flags.getNonZeroByValAlign(), in CreateCopyOfByValArgument()
402 const SDLoc &DL) const { in EmitTailCallLoadRetAddr()
407 OutRetAddr = DAG.getLoad(VT, DL, Chain, OutRetAddr, MachinePointerInfo()); in EmitTailCallLoadRetAddr()
413 EVT PtrVT, unsigned SlotSize, int FPDiff, const SDLoc &DL) const { in EmitTailCallStoreRetAddr()
424 Chain, DL, RetFI, NewFI, in EmitTailCallStoreRetAddr()
432 const SDLoc &DL, SelectionDAG &DAG, in LowerMemArgument() argument
492 ValVT, DL, Chain, FIN, in LowerMemArgument()
494 return VA.isExtInLoc() ? DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val) in LowerMemArgument()
500 SDValue Arg, const SDLoc &DL, in LowerMemOpCallTo() argument
505 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, DL); in LowerMemOpCallTo()
506 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), in LowerMemOpCallTo()
509 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, DL); in LowerMemOpCallTo()
512 Chain, DL, Arg, PtrOff, in LowerMemOpCallTo()
523 SDLoc &DL = CLI.DL; in LowerCall() local
624 NumBytes - NumBytesToPush, DL); in LowerCall()
629 Chain = EmitTailCallLoadRetAddr(DAG, RetFI, Chain, IsTailCall, FPDiff, DL); in LowerCall()
657 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, RegVT, Arg); in LowerCall()
660 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, RegVT, Arg); in LowerCall()
663 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
673 Chain, DL, Arg, SpillSlot, in LowerCall()
685 StackPtr = DAG.getCopyFromReg(Chain, DL, RegInfo->getStackRegister(), in LowerCall()
689 LowerMemOpCallTo(Chain, StackPtr, Arg, DL, DAG, VA, Flags)); in LowerCall()
694 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); in LowerCall()
703 SDValue Val = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT); in LowerCall()
741 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), DL); in LowerCall()
743 StackPtr = DAG.getCopyFromReg(Chain, DL, RegInfo->getStackRegister(), in LowerCall()
746 Source = DAG.getNode(ISD::ADD, DL, getPointerTy(DAG.getDataLayout()), in LowerCall()
750 CreateCopyOfByValArgument(Source, FIN, ArgChain, Flags, DAG, DL)); in LowerCall()
754 ArgChain, DL, Arg, FIN, in LowerCall()
760 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains2); in LowerCall()
765 Subtarget.getSlotSize(), FPDiff, DL); in LowerCall()
772 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[i].first, in LowerCall()
790 GV, DL, getPointerTy(DAG.getDataLayout()), G->getOffset(), OpFlags); in LowerCall()
795 Callee = DAG.getNode(M68kISD::WrapperPC, DL, in LowerCall()
800 getPointerTy(DAG.getDataLayout()), DL, DAG.getEntryNode(), Callee, in LowerCall()
818 Chain = DAG.getCALLSEQ_END(Chain, NumBytesToPop, 0, InGlue, DL); in LowerCall()
826 Ops.push_back(DAG.getConstant(FPDiff, DL, MVT::i32)); in LowerCall()
845 return DAG.getNode(M68kISD::TC_RETURN, DL, NodeTys, Ops); in LowerCall()
848 Chain = DAG.getNode(M68kISD::CALL, DL, NodeTys, Ops); in LowerCall()
873 InGlue, DL); in LowerCall()
879 return LowerCallResult(Chain, InGlue, CallConv, IsVarArg, Ins, DL, DAG, in LowerCall()
885 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerCallResult() argument
900 Chain = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), CopyVT, InGlue) in LowerCallResult()
905 Val = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Val); in LowerCallResult()
920 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, in LowerFormalArguments() argument
955 ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
961 ArgValue = DAG.getNode(ISD::AssertSext, DL, RegVT, ArgValue, in LowerFormalArguments()
964 ArgValue = DAG.getNode(ISD::AssertZext, DL, RegVT, ArgValue, in LowerFormalArguments()
971 ArgValue = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), ArgValue); in LowerFormalArguments()
975 ArgValue = LowerMemArgument(Chain, CCID, Ins, DL, DAG, VA, MFI, i); in LowerFormalArguments()
982 DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue, MachinePointerInfo()); in LowerFormalArguments()
1003 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), DL, Reg, InVals[i]); in LowerFormalArguments()
1004 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Copy, Chain); in LowerFormalArguments()
1036 SDValue RegVal = DAG.getCopyFromReg(Chain, DL, F.VReg, F.VT); in LowerFormalArguments()
1038 Chain = DAG.getCopyToReg(Chain, DL, F.VReg, RegVal); in LowerFormalArguments()
1075 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn() argument
1089 DAG.getTargetConstant(MFI->getBytesToPopOnReturn(), DL, MVT::i32)); in LowerReturn()
1100 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1102 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1105 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1107 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1111 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), ValToCopy, Glue); in LowerReturn()
1148 SDValue Val = DAG.getCopyFromReg(RetOps[0], DL, SRetReg, in LowerReturn()
1154 Chain = DAG.getCopyToReg(Chain, DL, RetValReg, Val, Glue); in LowerReturn()
1167 return DAG.getNode(M68kISD::RET, DL, MVT::Other, RetOps); in LowerReturn()
1557 SDLoc DL(Op); in lowerOverflowArithmetic() local
1566 LHS = DAG.getNode(ExtOp, DL, MVT::i16, LHS); in lowerOverflowArithmetic()
1567 RHS = DAG.getNode(ExtOp, DL, MVT::i16, RHS); in lowerOverflowArithmetic()
1615 SDValue Arith = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); in lowerOverflowArithmetic()
1619 Result = DAG.getNode(TruncOp, DL, MVT::i8, Arith); in lowerOverflowArithmetic()
1622 CCR = DAG.getConstant(0, DL, N->getValueType(1)); in lowerOverflowArithmetic()
1629 SDLoc DL(Op); in LowerXALUO() local
1644 Overflow = DAG.getNode(M68kISD::SETCC, DL, N->getValueType(1), in LowerXALUO()
1645 DAG.getConstant(CC, DL, MVT::i8), CCR); in LowerXALUO()
1648 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Result, Overflow); in LowerXALUO()
1654 const SDLoc &DL, SelectionDAG &DAG) { in getBitTestCondition() argument
1659 Src = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src); in getBitTestCondition()
1664 BitNo = DAG.getNode(ISD::ANY_EXTEND, DL, Src.getValueType(), BitNo); in getBitTestCondition()
1666 SDValue BTST = DAG.getNode(M68kISD::BTST, DL, MVT::i32, Src, BitNo); in getBitTestCondition()
1670 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in getBitTestCondition()
1671 DAG.getConstant(Cond, DL, MVT::i8), BTST); in getBitTestCondition()
1675 static SDValue LowerAndToBTST(SDValue And, ISD::CondCode CC, const SDLoc &DL, in LowerAndToBTST() argument
1713 RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), DL, LHS.getValueType()); in LowerAndToBTST()
1718 return getBitTestCondition(LHS, RHS, CC, DL, DAG); in LowerAndToBTST()
1753 static unsigned TranslateM68kCC(ISD::CondCode SetCCOpcode, const SDLoc &DL, in TranslateM68kCC() argument
1760 RHS = DAG.getConstant(0, DL, RHS.getValueType()); in TranslateM68kCC()
1769 RHS = DAG.getConstant(0, DL, RHS.getValueType()); in TranslateM68kCC()
1835 const SDLoc &DL, SelectionDAG &DAG) { in LowerTruncateToBTST() argument
1845 CC, DL, DAG); in LowerTruncateToBTST()
1868 const SDLoc &DL, SelectionDAG &DAG) const { in EmitTest() argument
1913 return DAG.getNode(M68kISD::CMP, DL, MVT::i8, in EmitTest()
1914 DAG.getConstant(0, DL, Op.getValueType()), Op); in EmitTest()
1968 Op = DAG.getNode(ISD::AND, DL, VT, Op->getOperand(0), in EmitTest()
1969 DAG.getConstant(Mask, DL, VT)); in EmitTest()
2062 SDValue V0 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(0)); in EmitTest()
2063 SDValue V1 = DAG.getNode(ISD::TRUNCATE, DL, VT, WideVal.getOperand(1)); in EmitTest()
2064 Op = DAG.getNode(ConvertedOp, DL, VT, V0, V1); in EmitTest()
2071 return DAG.getNode(M68kISD::CMP, DL, MVT::i8, in EmitTest()
2072 DAG.getConstant(0, DL, Op.getValueType()), Op); in EmitTest()
2077 SDValue New = DAG.getNode(Opcode, DL, VTs, Ops); in EmitTest()
2103 const SDLoc &DL, SelectionDAG &DAG) const { in EmitCmp() argument
2105 return EmitTest(Op0, M68kCC, DL, DAG); in EmitCmp()
2119 Op0 = DAG.getNode(ExtendOp, DL, MVT::i32, Op0); in EmitCmp()
2120 Op1 = DAG.getNode(ExtendOp, DL, MVT::i32, Op1); in EmitCmp()
2124 SDValue Sub = DAG.getNode(M68kISD::SUB, DL, VTs, Op0, Op1); in EmitCmp()
2127 return DAG.getNode(M68kISD::CMP, DL, MVT::i8, Op0, Op1); in EmitCmp()
2133 const SDLoc &DL, in LowerToBTST() argument
2136 return LowerAndToBTST(Op, CC, DL, DAG); in LowerToBTST()
2138 return LowerTruncateToBTST(Op, CC, DL, DAG); in LowerToBTST()
2148 SDLoc DL(Op); in LowerSETCC() local
2158 if (SDValue NewSetCC = LowerToBTST(Op0, CC, DL, DAG)) { in LowerSETCC()
2160 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, NewSetCC); in LowerSETCC()
2180 DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCC()
2181 DAG.getConstant(CCode, DL, MVT::i8), Op0.getOperand(1)); in LowerSETCC()
2183 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, SetCC); in LowerSETCC()
2190 return DAG.getSetCC(DL, VT, Op0, DAG.getConstant(0, DL, MVT::i1), NewCC); in LowerSETCC()
2193 SDValue Xor = DAG.getNode(ISD::XOR, DL, MVT::i1, Op0, Op1); in LowerSETCC()
2194 return DAG.getSetCC(DL, VT, Xor, DAG.getConstant(0, DL, MVT::i1), CC); in LowerSETCC()
2199 unsigned M68kCC = TranslateM68kCC(CC, DL, IsFP, Op0, Op1, DAG); in LowerSETCC()
2203 SDValue CCR = EmitCmp(Op0, Op1, M68kCC, DL, DAG); in LowerSETCC()
2204 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCC()
2205 DAG.getConstant(M68kCC, DL, MVT::i8), CCR); in LowerSETCC()
2214 SDLoc DL(Op); in LowerSETCCCARRY() local
2221 Carry = DAG.getNode(M68kISD::ADD, DL, DAG.getVTList(CarryVT, MVT::i32), Carry, in LowerSETCCCARRY()
2222 DAG.getConstant(NegOne, DL, CarryVT)); in LowerSETCCCARRY()
2226 DAG.getNode(M68kISD::SUBX, DL, VTs, LHS, RHS, Carry.getValue(1)); in LowerSETCCCARRY()
2228 return DAG.getNode(M68kISD::SETCC, DL, MVT::i8, in LowerSETCCCARRY()
2229 DAG.getConstant(CC, DL, MVT::i8), Cmp.getValue(1)); in LowerSETCCCARRY()
2265 SDLoc DL(Op); in LowerSELECT() local
2298 DAG.getNode(M68kISD::SUB, DL, VTs, in LowerSELECT()
2299 DAG.getConstant(0, DL, CmpOp0.getValueType()), CmpOp0); in LowerSELECT()
2301 SDValue Res = DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(), in LowerSELECT()
2302 DAG.getConstant(M68k::COND_CS, DL, MVT::i8), in LowerSELECT()
2307 Cmp = DAG.getNode(M68kISD::CMP, DL, MVT::i8, in LowerSELECT()
2308 DAG.getConstant(1, DL, CmpOp0.getValueType()), CmpOp0); in LowerSELECT()
2311 DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(), in LowerSELECT()
2312 DAG.getConstant(M68k::COND_CS, DL, MVT::i8), Cmp); in LowerSELECT()
2315 Res = DAG.getNOT(DL, Res, Res.getValueType()); in LowerSELECT()
2318 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); in LowerSELECT()
2349 CC = DAG.getConstant(CCode, DL, MVT::i8); in LowerSELECT()
2361 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) { in LowerSELECT()
2370 CC = DAG.getConstant(M68k::COND_NE, DL, MVT::i8); in LowerSELECT()
2371 Cond = EmitTest(Cond, M68k::COND_NE, DL, DAG); in LowerSELECT()
2385 DAG.getNode(M68kISD::SETCC_CARRY, DL, Op.getValueType(), in LowerSELECT()
2386 DAG.getConstant(M68k::COND_CS, DL, MVT::i8), Cond); in LowerSELECT()
2388 return DAG.getNOT(DL, Res, Res.getValueType()); in LowerSELECT()
2404 SDValue Cmov = DAG.getNode(M68kISD::CMOV, DL, VTs, T2, T1, CC, Cond); in LowerSELECT()
2405 return DAG.getNode(ISD::TRUNCATE, DL, Op.getValueType(), Cmov); in LowerSELECT()
2424 return DAG.getNode(M68kISD::CMOV, DL, VTs, Ops); in LowerSELECT()
2455 SDLoc DL(Op); in LowerBRCOND() local
2516 CC = DAG.getConstant(CCode, DL, MVT::i8); in LowerBRCOND()
2529 Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain, in LowerBRCOND()
2546 CC = DAG.getConstant(CCode, DL, MVT::i8); in LowerBRCOND()
2559 Chain = DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain, in LowerBRCOND()
2564 CC = DAG.getConstant(CCode, DL, MVT::i8); in LowerBRCOND()
2577 CC = DAG.getConstant(CCode, DL, MVT::i8); in LowerBRCOND()
2590 if (SDValue NewSetCC = LowerToBTST(Cond, ISD::SETNE, DL, DAG)) { in LowerBRCOND()
2600 CC = DAG.getConstant(MxCond, DL, MVT::i8); in LowerBRCOND()
2601 Cond = EmitTest(Cond, MxCond, DL, DAG); in LowerBRCOND()
2603 return DAG.getNode(M68kISD::BRCOND, DL, Op.getValueType(), Chain, Dest, CC, in LowerBRCOND()
2667 SDLoc DL(CP); in LowerConstantPool() local
2668 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result); in LowerConstantPool()
2672 Result = DAG.getNode(ISD::ADD, DL, PtrVT, in LowerConstantPool()
2697 SDLoc DL(Op); in LowerExternalSymbol() local
2698 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result); in LowerExternalSymbol()
2702 Result = DAG.getNode(ISD::ADD, DL, PtrVT, in LowerExternalSymbol()
2710 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result, in LowerExternalSymbol()
2722 SDLoc DL(Op); in LowerBlockAddress() local
2729 Result = DAG.getNode(M68kISD::WrapperPC, DL, PtrVT, Result); in LowerBlockAddress()
2731 Result = DAG.getNode(M68kISD::Wrapper, DL, PtrVT, Result); in LowerBlockAddress()
2737 DAG.getNode(ISD::ADD, DL, PtrVT, in LowerBlockAddress()
2738 DAG.getNode(M68kISD::GLOBAL_BASE_REG, DL, PtrVT), Result); in LowerBlockAddress()
2745 const SDLoc &DL, int64_t Offset, in LowerGlobalAddress() argument
2754 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Offset); in LowerGlobalAddress()
2757 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags); in LowerGlobalAddress()
2761 Result = DAG.getNode(M68kISD::WrapperPC, DL, PtrVT, Result); in LowerGlobalAddress()
2763 Result = DAG.getNode(M68kISD::Wrapper, DL, PtrVT, Result); in LowerGlobalAddress()
2768 DAG.getNode(ISD::ADD, DL, PtrVT, in LowerGlobalAddress()
2769 DAG.getNode(M68kISD::GLOBAL_BASE_REG, DL, PtrVT), Result); in LowerGlobalAddress()
2775 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result, in LowerGlobalAddress()
2782 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result, in LowerGlobalAddress()
2783 DAG.getConstant(Offset, DL, PtrVT)); in LowerGlobalAddress()
2815 SDLoc DL(JT); in LowerJumpTable() local
2816 Result = DAG.getNode(WrapperKind, DL, PtrVT, Result); in LowerJumpTable()
2820 Result = DAG.getNode(ISD::ADD, DL, PtrVT, in LowerJumpTable()
3101 DebugLoc DL = MI.getDebugLoc(); in EmitLoweredSelect() local
3240 BuildMI(MBB, DL, TII->get(Opc)).addMBB(SinkMBB); in EmitLoweredSelect()
3245 BuildMI(Jcc1MBB, DL, TII->get(Opc2)).addMBB(SinkMBB); in EmitLoweredSelect()
3288 BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(M68k::PHI), DestReg) in EmitLoweredSelect()
3304 DL, TII->get(TargetOpcode::COPY), in EmitLoweredSelect()
3344 SDLoc DL(Op); in LowerVASTART() local
3349 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), in LowerVASTART()
3385 SDLoc DL(Op); in LowerDYNAMIC_STACKALLOC() local
3396 Chain = DAG.getCALLSEQ_START(Chain, 0, 0, DL); in LowerDYNAMIC_STACKALLOC()
3404 Chain = DAG.getCopyToReg(Chain, DL, Vreg, Size); in LowerDYNAMIC_STACKALLOC()
3405 Result = DAG.getNode(M68kISD::SEG_ALLOCA, DL, SPTy, Chain, in LowerDYNAMIC_STACKALLOC()
3413 SDValue SP = DAG.getCopyFromReg(Chain, DL, SPReg, VT); in LowerDYNAMIC_STACKALLOC()
3417 Result = DAG.getNode(ISD::SUB, DL, VT, SP, Size); // Value in LowerDYNAMIC_STACKALLOC()
3419 Result = DAG.getNode(ISD::AND, DL, VT, Result, in LowerDYNAMIC_STACKALLOC()
3420 DAG.getConstant(-(uint64_t)Align, DL, VT)); in LowerDYNAMIC_STACKALLOC()
3421 Chain = DAG.getCopyToReg(Chain, DL, SPReg, Result); // Output chain in LowerDYNAMIC_STACKALLOC()
3424 Chain = DAG.getCALLSEQ_END(Chain, 0, 0, SDValue(), DL); in LowerDYNAMIC_STACKALLOC()
3427 return DAG.getMergeValues(Ops, DL); in LowerDYNAMIC_STACKALLOC()
3432 SDLoc DL(Op); in LowerShiftLeftParts() local
3445 SDValue Zero = DAG.getConstant(0, DL, VT); in LowerShiftLeftParts()
3446 SDValue One = DAG.getConstant(1, DL, VT); in LowerShiftLeftParts()
3447 SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT); in LowerShiftLeftParts()
3448 SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT); in LowerShiftLeftParts()
3450 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize); in LowerShiftLeftParts()
3452 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt); in LowerShiftLeftParts()
3454 SDValue LoTrue = DAG.getNode(ISD::SHL, DL, VT, Lo, Shamt); in LowerShiftLeftParts()
3455 SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, One); in LowerShiftLeftParts()
3457 DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, RegisterSizeMinus1Shamt); in LowerShiftLeftParts()
3458 SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, Hi, Shamt); in LowerShiftLeftParts()
3459 SDValue HiTrue = DAG.getNode(ISD::OR, DL, VT, ShiftLeftHi, ShiftRightLo); in LowerShiftLeftParts()
3460 SDValue HiFalse = DAG.getNode(ISD::SHL, DL, VT, Lo, ShamtMinusRegisterSize); in LowerShiftLeftParts()
3463 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftLeftParts()
3465 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, Zero); in LowerShiftLeftParts()
3466 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); in LowerShiftLeftParts()
3468 return DAG.getMergeValues({Lo, Hi}, DL); in LowerShiftLeftParts()
3473 SDLoc DL(Op); in LowerShiftRightParts() local
3497 SDValue Zero = DAG.getConstant(0, DL, VT); in LowerShiftRightParts()
3498 SDValue One = DAG.getConstant(1, DL, VT); in LowerShiftRightParts()
3499 SDValue MinusRegisterSize = DAG.getConstant(-32, DL, VT); in LowerShiftRightParts()
3500 SDValue RegisterSizeMinus1 = DAG.getConstant(32 - 1, DL, VT); in LowerShiftRightParts()
3502 DAG.getNode(ISD::ADD, DL, VT, Shamt, MinusRegisterSize); in LowerShiftRightParts()
3504 DAG.getNode(ISD::XOR, DL, VT, RegisterSizeMinus1, Shamt); in LowerShiftRightParts()
3506 SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, Lo, Shamt); in LowerShiftRightParts()
3507 SDValue ShiftLeftHi1 = DAG.getNode(ISD::SHL, DL, VT, Hi, One); in LowerShiftRightParts()
3509 DAG.getNode(ISD::SHL, DL, VT, ShiftLeftHi1, RegisterSizeMinus1Shamt); in LowerShiftRightParts()
3510 SDValue LoTrue = DAG.getNode(ISD::OR, DL, VT, ShiftRightLo, ShiftLeftHi); in LowerShiftRightParts()
3511 SDValue HiTrue = DAG.getNode(ShiftRightOp, DL, VT, Hi, Shamt); in LowerShiftRightParts()
3513 DAG.getNode(ShiftRightOp, DL, VT, Hi, ShamtMinusRegisterSize); in LowerShiftRightParts()
3515 IsSRA ? DAG.getNode(ISD::SRA, DL, VT, Hi, RegisterSizeMinus1) : Zero; in LowerShiftRightParts()
3518 DAG.getSetCC(DL, MVT::i8, ShamtMinusRegisterSize, Zero, ISD::SETLT); in LowerShiftRightParts()
3520 Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, LoTrue, LoFalse); in LowerShiftRightParts()
3521 Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, HiTrue, HiFalse); in LowerShiftRightParts()
3523 return DAG.getMergeValues({Lo, Hi}, DL); in LowerShiftRightParts()
3576 SDLoc DL(N); in combineM68kSetCC() local
3582 return getSETCC(CC, Flags, DL, DAG); in combineM68kSetCC()
3588 SDLoc DL(N); in combineM68kBrCond() local
3596 SDValue Cond = DAG.getConstant(CC, DL, MVT::i8); in combineM68kBrCond()
3597 return DAG.getNode(M68kISD::BRCOND, DL, N->getVTList(), N->getOperand(0), in combineM68kBrCond()