Searched refs:CheckAll (Results 1 – 15 of 15) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredNeoverse.td | 18 CheckAll<[CheckShiftLSL, 23 CheckAll<[ 38 CheckAll<[CheckOpcode<[ 51 CheckAll<[CheckOpcode< 62 CheckAll<[CheckOpcode<[MOVZWi, MOVZXi]>, 70 CheckAll<[CheckOpcode<[ORRWrs, ORRXrs]>, 71 CheckAll<[CheckIsReg1Zero, 77 CheckAll<[CheckOpcode<[FMOVWHr, FMOVXHr, 82 CheckAll<[CheckOpcode<[MOVID, MOVIv2d_ns]>,
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| H A D | AArch64SchedPredExynos.td | 18 CheckAll< 29 CheckAll<[CheckOpcode<[BLR]>, 40 CheckAll< 85 CheckAll<
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| H A D | AArch64SchedPredicates.td | 65 def CheckIsReg#I#Zero : CheckAll< 270 CheckAll< 289 CheckAll< 303 CheckAll< 317 CheckAll< 336 CheckAll< 344 CheckAll<[CheckOpcode<[EXTRWrri, EXTRXrri]>,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SchedPredicates.td | 23 def ZeroIdiomVPERMPredicate : CheckAll<[ 30 def IsThreeOperandsLEAPredicate: CheckAll<[ 41 CheckAll<[ 125 def IsAtomicCompareAndSwap_8 : CheckAll<[ 130 def IsAtomicCompareAndSwap : CheckAll<[ 135 def IsAtomicCompareAndSwap8B : CheckAll<[ 140 def IsAtomicCompareAndSwap16B : CheckAll<[
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| H A D | X86ScheduleBtVer2.td | 947 CheckAll<[
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| H A D | X86ScheduleBdVer2.td | 562 CheckAll<[
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| H A D | X86SchedHaswell.td | 1859 CheckAll<[
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| H A D | X86ScheduleZnver3.td | 589 CheckAll<[
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| H A D | X86ScheduleZnver4.td | 600 CheckAll<[
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| /freebsd/sys/dev/pms/RefTisa/sallsdk/spc/ |
| H A D | satimer.c | 142 saRoot->CheckAll++; in saTimerTick() 149 saRoot->CheckAll, in saTimerTick() 155 saRoot->CheckAll, in saTimerTick() 166 saRoot->CheckAll, in saTimerTick() 174 if( saRoot->CheckAll > 1) in saTimerTick() 196 if(saRoot->CheckAll ) in saTimerTick()
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| H A D | satypes.h | 335 bit32 CheckAll; member
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| H A D | saint.c | 872 else if (saRoot->CheckAll) in saDelayedInterruptHandler() 895 else if (saRoot->CheckAll) in saDelayedInterruptHandler() 905 saRoot->CheckAll = 0; in saDelayedInterruptHandler()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | TargetMacroFusion.td | 145 CheckAll<!listconcat( 148 CheckAll<!listconcat(
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| H A D | TargetInstrPredicate.td | 16 // def MCInstPredicateExample : CheckAll<[ 24 // The `CheckAll` from the example defines a composition of three different 220 // A sequence of predicates. It is used as the base class for CheckAll, and 227 class CheckAll<list<MCInstPredicate> Sequence> 239 : CheckAll<[CheckImmOperandGE<Index, Start>, CheckImmOperandLE<Index, End>]>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleA57.td | 24 def IsCPSRDefinedAndPredicated : CheckAll<[IsCPSRDefined, IsPredicated]>; 36 class Am3NegativeRegOffset<int n> : MCSchedPredicate<CheckAll<[ 48 CheckAll<[
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