1//===-- RISCVInstrPredicates.td - Instruction Predicates ---*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the RISC-V instruction predicates. 10// 11//===----------------------------------------------------------------------===// 12 13// This predicate is true when the rs2 operand of vlse or vsse is x0, false 14// otherwise. 15def VLDSX0Pred : MCSchedPredicate<CheckRegOperand<3, X0>>; 16 17// Returns true if this is the sext.w pattern, addiw rd, rs1, 0. 18def isSEXT_W 19 : TIIPredicate<"isSEXT_W", 20 MCReturnStatement<CheckAll<[ 21 CheckOpcode<[ADDIW]>, 22 CheckIsRegOperand<1>, 23 CheckIsImmOperand<2>, 24 CheckImmOperand<2, 0> 25 ]>>>; 26 27// Returns true if this is the zext.w pattern, adduw rd, rs1, x0. 28def isZEXT_W 29 : TIIPredicate<"isZEXT_W", 30 MCReturnStatement<CheckAll<[ 31 CheckOpcode<[ADD_UW]>, 32 CheckIsRegOperand<1>, 33 CheckIsRegOperand<2>, 34 CheckRegOperand<2, X0> 35 ]>>>; 36 37// Returns true if this is the zext.b pattern, andi rd, rs1, 255. 38def isZEXT_B 39 : TIIPredicate<"isZEXT_B", 40 MCReturnStatement<CheckAll<[ 41 CheckOpcode<[ANDI]>, 42 CheckIsRegOperand<1>, 43 CheckIsImmOperand<2>, 44 CheckImmOperand<2, 255> 45 ]>>>; 46 47def isSelectPseudo 48 : TIIPredicate<"isSelectPseudo", 49 MCReturnStatement< 50 CheckOpcode<[ 51 Select_GPR_Using_CC_GPR, 52 Select_GPR_Using_CC_SImm5_CV, 53 Select_GPRNoX0_Using_CC_SImm5NonZero_QC, 54 Select_GPRNoX0_Using_CC_UImm5NonZero_QC, 55 Select_GPRNoX0_Using_CC_SImm16NonZero_QC, 56 Select_GPRNoX0_Using_CC_UImm16NonZero_QC, 57 Select_GPR_Using_CC_UImmLog2XLen_NDS, 58 Select_GPR_Using_CC_UImm7_NDS, 59 Select_FPR16_Using_CC_GPR, 60 Select_FPR16INX_Using_CC_GPR, 61 Select_FPR32_Using_CC_GPR, 62 Select_FPR32INX_Using_CC_GPR, 63 Select_FPR64_Using_CC_GPR, 64 Select_FPR64INX_Using_CC_GPR, 65 Select_FPR64IN32X_Using_CC_GPR 66 ]>>>; 67 68// Returns true if this is a vector configuration instruction. 69def isVectorConfigInstr 70 : TIIPredicate<"isVectorConfigInstr", 71 MCReturnStatement< 72 CheckOpcode<[ 73 PseudoVSETVLI, 74 PseudoVSETVLIX0, 75 PseudoVSETVLIX0X0, 76 PseudoVSETIVLI 77 ]>>>; 78 79// Return true if this is 'vsetvli x0, x0, vtype' which preserves 80// VL and only sets VTYPE. 81def isVLPreservingConfig 82 : TIIPredicate<"isVLPreservingConfig", 83 MCReturnStatement<CheckOpcode<[PseudoVSETVLIX0X0]>>>; 84 85def isFloatScalarMoveOrScalarSplatInstr 86 : TIIPredicate<"isFloatScalarMoveOrScalarSplatInstr", 87 MCReturnStatement< 88 CheckOpcode<!listflatten([ 89 !instances<Pseudo>("^PseudoVFMV_S_F.*"), 90 !instances<Pseudo>("^PseudoVFMV_V_F.*") 91 ])>>>; 92 93def isScalarExtractInstr 94 : TIIPredicate<"isScalarExtractInstr", 95 MCReturnStatement< 96 CheckOpcode<!listflatten([ 97 !instances<Pseudo>("^PseudoVMV_X_S.*"), 98 !instances<Pseudo>("^PseudoVFMV_F.*_S.*") 99 ])>>>; 100 101def isVExtractInstr 102 : TIIPredicate<"isVExtractInstr", 103 MCReturnStatement< 104 CheckOpcode< 105 !instances<Instruction>("^PseudoRI_VEXTRACT.*")>>>; 106 107def isScalarInsertInstr 108 : TIIPredicate<"isScalarInsertInstr", 109 MCReturnStatement< 110 CheckOpcode<!listflatten([ 111 !instances<Pseudo>("^PseudoVMV_S_X.*"), 112 !instances<Pseudo>("^PseudoVFMV_S_F.*") 113 ])>>>; 114 115def isScalarSplatInstr 116 : TIIPredicate<"isScalarSplatInstr", 117 MCReturnStatement< 118 CheckOpcode<!listflatten([ 119 !instances<Pseudo>("^PseudoVMV_V_I.*"), 120 !instances<Pseudo>("^PseudoVMV_V_X.*"), 121 !instances<Pseudo>("^PseudoVFMV_V_F.*") 122 ])>>>; 123 124def isVSlideInstr 125 : TIIPredicate<"isVSlideInstr", 126 MCReturnStatement< 127 CheckOpcode<!listflatten([ 128 !instances<Pseudo>("^PseudoVSLIDEDOWN_VX.*"), 129 !instances<Pseudo>("^PseudoVSLIDEDOWN_VI.*"), 130 !instances<Pseudo>("^PseudoVSLIDEUP_VX.*"), 131 !instances<Pseudo>("^PseudoVSLIDEUP_VI.*") 132 ])>>>; 133 134def isFaultOnlyFirstLoad 135 : TIIPredicate<"isFaultOnlyFirstLoad", 136 MCReturnStatement< 137 CheckOpcode< 138 !instances<Pseudo>( 139 "^PseudoVL(SEG[2-8])?E(8|16|32|64)FF_V.*")>>>; 140 141def isNonZeroLoadImmediate 142 : TIIPredicate<"isNonZeroLoadImmediate", 143 MCReturnStatement<CheckAll<[ 144 CheckOpcode<[ADDI]>, 145 CheckIsRegOperand<1>, 146 CheckRegOperand<1, X0>, 147 CheckIsImmOperand<2>, 148 CheckNot<CheckImmOperand<2, 0>> 149 ]>>>; 150 151def ignoresVXRM 152 : TIIPredicate<"ignoresVXRM", 153 MCOpcodeSwitchStatement< 154 [MCOpcodeSwitchCase< 155 !listflatten([ 156 !instances<Pseudo>("^PseudoVNCLIP_WI.*"), 157 !instances<Pseudo>("^PseudoVNCLIPU_WI.*") 158 ]), 159 MCReturnStatement<CheckImmOperand<3, 0>>>], 160 MCReturnStatement<FalsePred>>>; 161