1*700637cbSDimitry Andric//===-- RISCVInstrPredicates.td - Instruction Predicates ---*- tablegen -*-===// 2*700637cbSDimitry Andric// 3*700637cbSDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*700637cbSDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*700637cbSDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*700637cbSDimitry Andric// 7*700637cbSDimitry Andric//===----------------------------------------------------------------------===// 8*700637cbSDimitry Andric// 9*700637cbSDimitry Andric// This file describes the RISC-V instruction predicates. 10*700637cbSDimitry Andric// 11*700637cbSDimitry Andric//===----------------------------------------------------------------------===// 12*700637cbSDimitry Andric 13*700637cbSDimitry Andric// This predicate is true when the rs2 operand of vlse or vsse is x0, false 14*700637cbSDimitry Andric// otherwise. 15*700637cbSDimitry Andricdef VLDSX0Pred : MCSchedPredicate<CheckRegOperand<3, X0>>; 16*700637cbSDimitry Andric 17*700637cbSDimitry Andric// Returns true if this is the sext.w pattern, addiw rd, rs1, 0. 18*700637cbSDimitry Andricdef isSEXT_W 19*700637cbSDimitry Andric : TIIPredicate<"isSEXT_W", 20*700637cbSDimitry Andric MCReturnStatement<CheckAll<[ 21*700637cbSDimitry Andric CheckOpcode<[ADDIW]>, 22*700637cbSDimitry Andric CheckIsRegOperand<1>, 23*700637cbSDimitry Andric CheckIsImmOperand<2>, 24*700637cbSDimitry Andric CheckImmOperand<2, 0> 25*700637cbSDimitry Andric ]>>>; 26*700637cbSDimitry Andric 27*700637cbSDimitry Andric// Returns true if this is the zext.w pattern, adduw rd, rs1, x0. 28*700637cbSDimitry Andricdef isZEXT_W 29*700637cbSDimitry Andric : TIIPredicate<"isZEXT_W", 30*700637cbSDimitry Andric MCReturnStatement<CheckAll<[ 31*700637cbSDimitry Andric CheckOpcode<[ADD_UW]>, 32*700637cbSDimitry Andric CheckIsRegOperand<1>, 33*700637cbSDimitry Andric CheckIsRegOperand<2>, 34*700637cbSDimitry Andric CheckRegOperand<2, X0> 35*700637cbSDimitry Andric ]>>>; 36*700637cbSDimitry Andric 37*700637cbSDimitry Andric// Returns true if this is the zext.b pattern, andi rd, rs1, 255. 38*700637cbSDimitry Andricdef isZEXT_B 39*700637cbSDimitry Andric : TIIPredicate<"isZEXT_B", 40*700637cbSDimitry Andric MCReturnStatement<CheckAll<[ 41*700637cbSDimitry Andric CheckOpcode<[ANDI]>, 42*700637cbSDimitry Andric CheckIsRegOperand<1>, 43*700637cbSDimitry Andric CheckIsImmOperand<2>, 44*700637cbSDimitry Andric CheckImmOperand<2, 255> 45*700637cbSDimitry Andric ]>>>; 46*700637cbSDimitry Andric 47*700637cbSDimitry Andricdef isSelectPseudo 48*700637cbSDimitry Andric : TIIPredicate<"isSelectPseudo", 49*700637cbSDimitry Andric MCReturnStatement< 50*700637cbSDimitry Andric CheckOpcode<[ 51*700637cbSDimitry Andric Select_GPR_Using_CC_GPR, 52*700637cbSDimitry Andric Select_GPR_Using_CC_SImm5_CV, 53*700637cbSDimitry Andric Select_GPRNoX0_Using_CC_SImm5NonZero_QC, 54*700637cbSDimitry Andric Select_GPRNoX0_Using_CC_UImm5NonZero_QC, 55*700637cbSDimitry Andric Select_GPRNoX0_Using_CC_SImm16NonZero_QC, 56*700637cbSDimitry Andric Select_GPRNoX0_Using_CC_UImm16NonZero_QC, 57*700637cbSDimitry Andric Select_GPR_Using_CC_UImmLog2XLen_NDS, 58*700637cbSDimitry Andric Select_GPR_Using_CC_UImm7_NDS, 59*700637cbSDimitry Andric Select_FPR16_Using_CC_GPR, 60*700637cbSDimitry Andric Select_FPR16INX_Using_CC_GPR, 61*700637cbSDimitry Andric Select_FPR32_Using_CC_GPR, 62*700637cbSDimitry Andric Select_FPR32INX_Using_CC_GPR, 63*700637cbSDimitry Andric Select_FPR64_Using_CC_GPR, 64*700637cbSDimitry Andric Select_FPR64INX_Using_CC_GPR, 65*700637cbSDimitry Andric Select_FPR64IN32X_Using_CC_GPR 66*700637cbSDimitry Andric ]>>>; 67*700637cbSDimitry Andric 68*700637cbSDimitry Andric// Returns true if this is a vector configuration instruction. 69*700637cbSDimitry Andricdef isVectorConfigInstr 70*700637cbSDimitry Andric : TIIPredicate<"isVectorConfigInstr", 71*700637cbSDimitry Andric MCReturnStatement< 72*700637cbSDimitry Andric CheckOpcode<[ 73*700637cbSDimitry Andric PseudoVSETVLI, 74*700637cbSDimitry Andric PseudoVSETVLIX0, 75*700637cbSDimitry Andric PseudoVSETVLIX0X0, 76*700637cbSDimitry Andric PseudoVSETIVLI 77*700637cbSDimitry Andric ]>>>; 78*700637cbSDimitry Andric 79*700637cbSDimitry Andric// Return true if this is 'vsetvli x0, x0, vtype' which preserves 80*700637cbSDimitry Andric// VL and only sets VTYPE. 81*700637cbSDimitry Andricdef isVLPreservingConfig 82*700637cbSDimitry Andric : TIIPredicate<"isVLPreservingConfig", 83*700637cbSDimitry Andric MCReturnStatement<CheckOpcode<[PseudoVSETVLIX0X0]>>>; 84*700637cbSDimitry Andric 85*700637cbSDimitry Andricdef isFloatScalarMoveOrScalarSplatInstr 86*700637cbSDimitry Andric : TIIPredicate<"isFloatScalarMoveOrScalarSplatInstr", 87*700637cbSDimitry Andric MCReturnStatement< 88*700637cbSDimitry Andric CheckOpcode<!listflatten([ 89*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVFMV_S_F.*"), 90*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVFMV_V_F.*") 91*700637cbSDimitry Andric ])>>>; 92*700637cbSDimitry Andric 93*700637cbSDimitry Andricdef isScalarExtractInstr 94*700637cbSDimitry Andric : TIIPredicate<"isScalarExtractInstr", 95*700637cbSDimitry Andric MCReturnStatement< 96*700637cbSDimitry Andric CheckOpcode<!listflatten([ 97*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVMV_X_S.*"), 98*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVFMV_F.*_S.*") 99*700637cbSDimitry Andric ])>>>; 100*700637cbSDimitry Andric 101*700637cbSDimitry Andricdef isVExtractInstr 102*700637cbSDimitry Andric : TIIPredicate<"isVExtractInstr", 103*700637cbSDimitry Andric MCReturnStatement< 104*700637cbSDimitry Andric CheckOpcode< 105*700637cbSDimitry Andric !instances<Instruction>("^PseudoRI_VEXTRACT.*")>>>; 106*700637cbSDimitry Andric 107*700637cbSDimitry Andricdef isScalarInsertInstr 108*700637cbSDimitry Andric : TIIPredicate<"isScalarInsertInstr", 109*700637cbSDimitry Andric MCReturnStatement< 110*700637cbSDimitry Andric CheckOpcode<!listflatten([ 111*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVMV_S_X.*"), 112*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVFMV_S_F.*") 113*700637cbSDimitry Andric ])>>>; 114*700637cbSDimitry Andric 115*700637cbSDimitry Andricdef isScalarSplatInstr 116*700637cbSDimitry Andric : TIIPredicate<"isScalarSplatInstr", 117*700637cbSDimitry Andric MCReturnStatement< 118*700637cbSDimitry Andric CheckOpcode<!listflatten([ 119*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVMV_V_I.*"), 120*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVMV_V_X.*"), 121*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVFMV_V_F.*") 122*700637cbSDimitry Andric ])>>>; 123*700637cbSDimitry Andric 124*700637cbSDimitry Andricdef isVSlideInstr 125*700637cbSDimitry Andric : TIIPredicate<"isVSlideInstr", 126*700637cbSDimitry Andric MCReturnStatement< 127*700637cbSDimitry Andric CheckOpcode<!listflatten([ 128*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVSLIDEDOWN_VX.*"), 129*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVSLIDEDOWN_VI.*"), 130*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVSLIDEUP_VX.*"), 131*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVSLIDEUP_VI.*") 132*700637cbSDimitry Andric ])>>>; 133*700637cbSDimitry Andric 134*700637cbSDimitry Andricdef isFaultOnlyFirstLoad 135*700637cbSDimitry Andric : TIIPredicate<"isFaultOnlyFirstLoad", 136*700637cbSDimitry Andric MCReturnStatement< 137*700637cbSDimitry Andric CheckOpcode< 138*700637cbSDimitry Andric !instances<Pseudo>( 139*700637cbSDimitry Andric "^PseudoVL(SEG[2-8])?E(8|16|32|64)FF_V.*")>>>; 140*700637cbSDimitry Andric 141*700637cbSDimitry Andricdef isNonZeroLoadImmediate 142*700637cbSDimitry Andric : TIIPredicate<"isNonZeroLoadImmediate", 143*700637cbSDimitry Andric MCReturnStatement<CheckAll<[ 144*700637cbSDimitry Andric CheckOpcode<[ADDI]>, 145*700637cbSDimitry Andric CheckIsRegOperand<1>, 146*700637cbSDimitry Andric CheckRegOperand<1, X0>, 147*700637cbSDimitry Andric CheckIsImmOperand<2>, 148*700637cbSDimitry Andric CheckNot<CheckImmOperand<2, 0>> 149*700637cbSDimitry Andric ]>>>; 150*700637cbSDimitry Andric 151*700637cbSDimitry Andricdef ignoresVXRM 152*700637cbSDimitry Andric : TIIPredicate<"ignoresVXRM", 153*700637cbSDimitry Andric MCOpcodeSwitchStatement< 154*700637cbSDimitry Andric [MCOpcodeSwitchCase< 155*700637cbSDimitry Andric !listflatten([ 156*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVNCLIP_WI.*"), 157*700637cbSDimitry Andric !instances<Pseudo>("^PseudoVNCLIPU_WI.*") 158*700637cbSDimitry Andric ]), 159*700637cbSDimitry Andric MCReturnStatement<CheckImmOperand<3, 0>>>], 160*700637cbSDimitry Andric MCReturnStatement<FalsePred>>>; 161