10b57cec5SDimitry Andric//===- AArch64SchedPredExynos.td - AArch64 Sched Preds -----*- tablegen -*-===// 20b57cec5SDimitry Andric// 30b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 40b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 50b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60b57cec5SDimitry Andric// 70b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 80b57cec5SDimitry Andric// 90b57cec5SDimitry Andric// This file defines scheduling predicate definitions that are used by the 100b57cec5SDimitry Andric// AArch64 Exynos processors. 110b57cec5SDimitry Andric// 120b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 130b57cec5SDimitry Andric 140b57cec5SDimitry Andric// Auxiliary predicates. 150b57cec5SDimitry Andric 160b57cec5SDimitry Andric// Check the shift in arithmetic and logic instructions. 170b57cec5SDimitry Andricdef ExynosCheckShift : CheckAny<[CheckShiftBy0, 180b57cec5SDimitry Andric CheckAll< 190b57cec5SDimitry Andric [CheckShiftLSL, 200b57cec5SDimitry Andric CheckAny< 210b57cec5SDimitry Andric [CheckShiftBy1, 220b57cec5SDimitry Andric CheckShiftBy2, 230b57cec5SDimitry Andric CheckShiftBy3]>]>]>; 240b57cec5SDimitry Andric 250b57cec5SDimitry Andric// Exynos predicates. 260b57cec5SDimitry Andric 270b57cec5SDimitry Andric// Identify BLR specifying the LR register as the indirect target register. 280b57cec5SDimitry Andricdef ExynosBranchLinkLRPred : MCSchedPredicate< 290b57cec5SDimitry Andric CheckAll<[CheckOpcode<[BLR]>, 300b57cec5SDimitry Andric CheckRegOperand<0, LR>]>>; 310b57cec5SDimitry Andric 320b57cec5SDimitry Andric// Identify arithmetic instructions without or with limited extension or shift. 330b57cec5SDimitry Andricdef ExynosArithFn : TIIPredicate< 340b57cec5SDimitry Andric "isExynosArithFast", 350b57cec5SDimitry Andric MCOpcodeSwitchStatement< 360b57cec5SDimitry Andric [MCOpcodeSwitchCase< 370b57cec5SDimitry Andric IsArithExtOp.ValidOpcodes, 380b57cec5SDimitry Andric MCReturnStatement< 390b57cec5SDimitry Andric CheckAny<[CheckExtBy0, 400b57cec5SDimitry Andric CheckAll< 410b57cec5SDimitry Andric [CheckAny< 420b57cec5SDimitry Andric [CheckExtUXTW, 430b57cec5SDimitry Andric CheckExtUXTX]>, 440b57cec5SDimitry Andric CheckAny< 450b57cec5SDimitry Andric [CheckExtBy1, 460b57cec5SDimitry Andric CheckExtBy2, 470b57cec5SDimitry Andric CheckExtBy3]>]>]>>>, 480b57cec5SDimitry Andric MCOpcodeSwitchCase< 490b57cec5SDimitry Andric IsArithShiftOp.ValidOpcodes, 500b57cec5SDimitry Andric MCReturnStatement<ExynosCheckShift>>, 510b57cec5SDimitry Andric MCOpcodeSwitchCase< 520b57cec5SDimitry Andric IsArithUnshiftOp.ValidOpcodes, 53480093f4SDimitry Andric MCReturnStatement<TruePred>>, 54480093f4SDimitry Andric MCOpcodeSwitchCase< 55480093f4SDimitry Andric IsArithImmOp.ValidOpcodes, 560b57cec5SDimitry Andric MCReturnStatement<TruePred>>], 570b57cec5SDimitry Andric MCReturnStatement<FalsePred>>>; 580b57cec5SDimitry Andricdef ExynosArithPred : MCSchedPredicate<ExynosArithFn>; 590b57cec5SDimitry Andric 600b57cec5SDimitry Andric// Identify logic instructions with limited shift. 610b57cec5SDimitry Andricdef ExynosLogicFn : TIIPredicate< 620b57cec5SDimitry Andric "isExynosLogicFast", 630b57cec5SDimitry Andric MCOpcodeSwitchStatement< 640b57cec5SDimitry Andric [MCOpcodeSwitchCase< 650b57cec5SDimitry Andric IsLogicShiftOp.ValidOpcodes, 660b57cec5SDimitry Andric MCReturnStatement<ExynosCheckShift>>, 670b57cec5SDimitry Andric MCOpcodeSwitchCase< 680b57cec5SDimitry Andric IsLogicUnshiftOp.ValidOpcodes, 69480093f4SDimitry Andric MCReturnStatement<TruePred>>, 70480093f4SDimitry Andric MCOpcodeSwitchCase< 71480093f4SDimitry Andric IsLogicImmOp.ValidOpcodes, 720b57cec5SDimitry Andric MCReturnStatement<TruePred>>], 730b57cec5SDimitry Andric MCReturnStatement<FalsePred>>>; 740b57cec5SDimitry Andricdef ExynosLogicPred : MCSchedPredicate<ExynosLogicFn>; 750b57cec5SDimitry Andric 760b57cec5SDimitry Andric// Identify more logic instructions with limited shift. 770b57cec5SDimitry Andricdef ExynosLogicExFn : TIIPredicate< 780b57cec5SDimitry Andric "isExynosLogicExFast", 790b57cec5SDimitry Andric MCOpcodeSwitchStatement< 800b57cec5SDimitry Andric [MCOpcodeSwitchCase< 810b57cec5SDimitry Andric IsLogicShiftOp.ValidOpcodes, 820b57cec5SDimitry Andric MCReturnStatement< 830b57cec5SDimitry Andric CheckAny< 840b57cec5SDimitry Andric [ExynosCheckShift, 850b57cec5SDimitry Andric CheckAll< 860b57cec5SDimitry Andric [CheckShiftLSL, 870b57cec5SDimitry Andric CheckShiftBy8]>]>>>, 880b57cec5SDimitry Andric MCOpcodeSwitchCase< 890b57cec5SDimitry Andric IsLogicUnshiftOp.ValidOpcodes, 90480093f4SDimitry Andric MCReturnStatement<TruePred>>, 91480093f4SDimitry Andric MCOpcodeSwitchCase< 92480093f4SDimitry Andric IsLogicImmOp.ValidOpcodes, 930b57cec5SDimitry Andric MCReturnStatement<TruePred>>], 940b57cec5SDimitry Andric MCReturnStatement<FalsePred>>>; 950b57cec5SDimitry Andricdef ExynosLogicExPred : MCSchedPredicate<ExynosLogicExFn>; 960b57cec5SDimitry Andric 970b57cec5SDimitry Andric// Identify a load or store using the register offset addressing mode 980b57cec5SDimitry Andric// with a scaled non-extended register. 990b57cec5SDimitry Andricdef ExynosScaledIdxFn : TIIPredicate<"isExynosScaledAddr", 1000b57cec5SDimitry Andric MCOpcodeSwitchStatement< 1010b57cec5SDimitry Andric [MCOpcodeSwitchCase< 1020b57cec5SDimitry Andric IsLoadStoreRegOffsetOp.ValidOpcodes, 1030b57cec5SDimitry Andric MCReturnStatement< 1040b57cec5SDimitry Andric CheckAny< 1050b57cec5SDimitry Andric [CheckMemExtSXTW, 1060b57cec5SDimitry Andric CheckMemExtUXTW, 1070b57cec5SDimitry Andric CheckMemScaled]>>>], 1080b57cec5SDimitry Andric MCReturnStatement<FalsePred>>>; 1090b57cec5SDimitry Andricdef ExynosScaledIdxPred : MCSchedPredicate<ExynosScaledIdxFn>; 1100b57cec5SDimitry Andric 1110b57cec5SDimitry Andric// Identify FP instructions. 11281ad6265SDimitry Andricdef ExynosFPPred : MCSchedPredicate<CheckFpOrNEON>; 1130b57cec5SDimitry Andric 1140b57cec5SDimitry Andric// Identify 128-bit NEON instructions. 1150b57cec5SDimitry Andricdef ExynosQFormPred : MCSchedPredicate<CheckQForm>; 1160b57cec5SDimitry Andric 1170b57cec5SDimitry Andric// Identify instructions that reset a register efficiently. 1180b57cec5SDimitry Andricdef ExynosResetFn : TIIPredicate< 1190b57cec5SDimitry Andric "isExynosResetFast", 1200b57cec5SDimitry Andric MCOpcodeSwitchStatement< 1210b57cec5SDimitry Andric [MCOpcodeSwitchCase< 1220b57cec5SDimitry Andric [ADR, ADRP, 1230b57cec5SDimitry Andric MOVNWi, MOVNXi, 1240b57cec5SDimitry Andric MOVZWi, MOVZXi], 1250b57cec5SDimitry Andric MCReturnStatement<TruePred>>, 1260b57cec5SDimitry Andric MCOpcodeSwitchCase< 1270b57cec5SDimitry Andric [ORRWri, ORRXri], 128*06c3fb27SDimitry Andric MCReturnStatement<CheckIsReg1Zero>>], 1290b57cec5SDimitry Andric MCReturnStatement< 1300b57cec5SDimitry Andric CheckAny< 1310b57cec5SDimitry Andric [IsCopyIdiomFn, 1320b57cec5SDimitry Andric IsZeroFPIdiomFn]>>>>; 1330b57cec5SDimitry Andricdef ExynosResetPred : MCSchedPredicate<ExynosResetFn>; 1340b57cec5SDimitry Andric 1350b57cec5SDimitry Andric// Identify cheap arithmetic and logic immediate instructions. 1360b57cec5SDimitry Andricdef ExynosCheapFn : TIIPredicate< 1370b57cec5SDimitry Andric "isExynosCheapAsMove", 1380b57cec5SDimitry Andric MCOpcodeSwitchStatement< 1390b57cec5SDimitry Andric [MCOpcodeSwitchCase< 1400b57cec5SDimitry Andric IsArithLogicImmOp.ValidOpcodes, 1410b57cec5SDimitry Andric MCReturnStatement<TruePred>>], 1420b57cec5SDimitry Andric MCReturnStatement< 1430b57cec5SDimitry Andric CheckAny< 1440b57cec5SDimitry Andric [ExynosArithFn, ExynosResetFn, ExynosLogicFn]>>>>; 145