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/linux/Documentation/devicetree/bindings/net/can/
H A Dxilinx,can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
16 - xlnx,zynq-can-1.0
17 - xlnx,axi-can-1.00.a
18 - xlnx,canfd-1.0
19 - xlnx,canfd-2.0
31 clock-names:
34 power-domains:
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/linux/drivers/mailbox/
H A Dmailbox.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Mailbox: Common code for Mailbox controllers and users
5 * Copyright (C) 2013-2014 Linaro Ltd.
22 #include "mailbox.h"
32 spin_lock_irqsave(&chan->lock, flags); in add_to_rbuf()
35 if (chan->msg_count == MBOX_TX_QUEUE_LEN) { in add_to_rbuf()
36 spin_unlock_irqrestore(&chan->lock, flags); in add_to_rbuf()
37 return -ENOBUFS; in add_to_rbuf()
40 idx = chan->msg_free; in add_to_rbuf()
41 chan->msg_data[idx] = mssg; in add_to_rbuf()
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H A Dbcm-pdc-mailbox.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Broadcom PDC Mailbox Driver
9 * offload engines. For example, the PDC driver works with both SPU-M and SPU2
13 * The PDC driver registers with the Linux mailbox framework as a mailbox
15 * a mailbox channel. The PDC driver uses interrupts to determine when data
25 * descriptors from the tx and rx ring, thus processing one response at a time.
41 #include <linux/mailbox/brcm-message.h>
43 #include <linux/dma-direction.h>
44 #include <linux/dma-mapping.h>
55 * Minimum number of ring descriptor entries that must be free to tell mailbox
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H A Dmailbox-test.c1 // SPDX-License-Identifier: GPL-2.0-or-later
51 size_t count, loff_t *ppos) in mbox_test_signal_write() argument
53 struct mbox_test_device *tdev = filp->private_data; in mbox_test_signal_write()
55 if (!tdev->tx_channel) { in mbox_test_signal_write()
56 dev_err(tdev->dev, "Channel cannot do Tx\n"); in mbox_test_signal_write()
57 return -EINVAL; in mbox_test_signal_write()
60 if (count > MBOX_MAX_SIG_LEN) { in mbox_test_signal_write()
61 dev_err(tdev->dev, in mbox_test_signal_write()
63 count, MBOX_MAX_SIG_LEN); in mbox_test_signal_write()
64 return -EINVAL; in mbox_test_signal_write()
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H A Darm_mhuv2.c1 // SPDX-License-Identifier: GPL-2.0
8 * An MHUv2 mailbox controller can provide up to 124 channel windows (each 32
10 * protocol modes: data-transfer and doorbell, to be used on those channel
18 * The number of registered mailbox channels is dependent on both the underlying
19 * hardware - mainly the number of channel windows implemented by the platform,
25 * for each mailbox controller, a sender device and a receiver device.
31 #include <linux/mailbox/arm_mhuv2_message.h>
45 #define LSB_MASK(n) ((1 << (n * __CHAR_BIT__)) - 1)
46 #define MHUV2_PROTOCOL_PROP "arm,mhuv2-protocols"
94 u8 pad1[0x0C - 0x04];
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/linux/drivers/net/ethernet/intel/idpf/
H A Didpf.h1 /* SPDX-License-Identifier: GPL-2.0-only */
25 #define GETMAXVAL(num_bits) GENMASK((num_bits) - 1, 0)
29 /* Default Mailbox settings */
31 #define IDPF_NUM_DFLT_MBX_Q 2 /* includes both TX and RX */
33 #define IDPF_DFLT_MBX_ID -1
34 /* maximum number of times to try before resetting mailbox */
37 ((IDPF_CTLQ_MAX_BUF_LEN - (struct_sz)) / (chunk_sz))
64 * enum idpf_state - State machine to handle bring up
78 * enum idpf_flags - Hard reset causes.
83 * @IDPF_MB_INTR_MODE: Mailbox in interrupt mode
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/linux/drivers/net/ethernet/intel/fm10k/
H A Dfm10k_pci.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
15 * fm10k_pci_tbl - PCI Device ID Table
35 struct fm10k_intfc *interface = hw->back; in fm10k_read_pci_cfg_word()
38 if (FM10K_REMOVED(hw->hw_addr)) in fm10k_read_pci_cfg_word()
41 pci_read_config_word(interface->pdev, reg, &value); in fm10k_read_pci_cfg_word()
50 u32 __iomem *hw_addr = READ_ONCE(hw->hw_addr); in fm10k_read_reg()
58 struct fm10k_intfc *interface = hw->back; in fm10k_read_reg()
59 struct net_device *netdev = interface->netdev; in fm10k_read_reg()
61 hw->hw_addr = NULL; in fm10k_read_reg()
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H A Dfm10k_common.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
7 * fm10k_get_bus_info_generic - Generic set PCI bus info
22 hw->bus_caps.width = fm10k_bus_width_pcie_x1; in fm10k_get_bus_info_generic()
25 hw->bus_caps.width = fm10k_bus_width_pcie_x2; in fm10k_get_bus_info_generic()
28 hw->bus_caps.width = fm10k_bus_width_pcie_x4; in fm10k_get_bus_info_generic()
31 hw->bus_caps.width = fm10k_bus_width_pcie_x8; in fm10k_get_bus_info_generic()
34 hw->bus_caps.width = fm10k_bus_width_unknown; in fm10k_get_bus_info_generic()
40 hw->bus_caps.speed = fm10k_bus_speed_2500; in fm10k_get_bus_info_generic()
43 hw->bus_caps.speed = fm10k_bus_speed_5000; in fm10k_get_bus_info_generic()
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H A Dfm10k_netdev.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
10 * fm10k_setup_tx_resources - allocate Tx resources (Descriptors)
11 * @tx_ring: tx descriptor ring (for a specific queue) to setup
17 struct device *dev = tx_ring->dev; in fm10k_setup_tx_resources()
20 size = sizeof(struct fm10k_tx_buffer) * tx_ring->count; in fm10k_setup_tx_resources()
22 tx_ring->tx_buffer = vzalloc(size); in fm10k_setup_tx_resources()
23 if (!tx_ring->tx_buffer) in fm10k_setup_tx_resources()
26 u64_stats_init(&tx_ring->syncp); in fm10k_setup_tx_resources()
29 tx_ring->size = tx_ring->count * sizeof(struct fm10k_tx_desc); in fm10k_setup_tx_resources()
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H A Dfm10k_pf.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
9 * fm10k_reset_hw_pf - PF hardware reset
28 /* We assume here Tx and Rx queue 0 are owned by the PF */ in fm10k_reset_hw_pf()
39 hw->mac.reset_while_pending++; in fm10k_reset_hw_pf()
68 * fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support
81 * fm10k_init_hw_pf - PF hardware initialization
107 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1); in fm10k_init_hw_pf()
114 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT); in fm10k_init_hw_pf()
139 switch (hw->bus.speed) { in fm10k_init_hw_pf()
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H A Dfm10k_vf.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2019 Intel Corporation. */
8 * fm10k_stop_hw_vf - Stop Tx/Rx units
14 u8 *perm_addr = hw->mac.perm_addr; in fm10k_stop_hw_vf()
36 tdlen = hw->mac.itr_scale << FM10K_TDLEN_ITR_SCALE_SHIFT; in fm10k_stop_hw_vf()
41 for (i = 0; i < hw->mac.max_queues; i++) { in fm10k_stop_hw_vf()
46 /* Restore ITR scale in software-defined mechanism in TDLEN in fm10k_stop_hw_vf()
58 * fm10k_reset_hw_vf - VF hardware reset
71 hw->mac.reset_while_pending++; in fm10k_reset_hw_vf()
91 * fm10k_init_hw_vf - VF hardware initialization
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/linux/drivers/net/ethernet/netronome/nfp/
H A Dnfp_net_ctrl.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
17 /* 64-bit per app capabilities */
23 * THB-350, 32k needs to be reserved.
51 #define NFP_NET_META_IPSEC 9 /* IPsec SA index for tx and rx */
61 /* Hash type pre-pended when a RSS hash was computed */
74 * %NFP_NET_TXR_MAX: Maximum number of TX rings
80 /* Read/Write config words (0x0000 - 0x002c)
83 * %NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings
87 * %NFP_NET_CFG_EXN: MSI-X table entry for exceptions
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H A Dnfp_net.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
21 #include <linux/io-64-nonatomic-hi-lo.h>
32 if (__nn->dp.netdev) \
33 netdev_printk(lvl, __nn->dp.netdev, fmt, ## args); \
35 dev_printk(lvl, __nn->dp.dev, "ctrl: " fmt, ## args); \
48 if (__dp->netdev) \
49 netdev_warn(__dp->netdev, fmt, ## args); \
51 dev_warn(__dp->dev, fmt, ## args); \
79 #define NFP_NET_MAX_TX_RINGS 64 /* Max. # of Tx rings per device */
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/linux/drivers/dma/
H A Dbcm-sba-raid.c1 // SPDX-License-Identifier: GPL-2.0-only
11 * SoC specific ring manager driver is implemented as a mailbox controller
19 * hardware devices for achieving high through-put.
22 * except submitting request to SBA hardware device via mailbox channels.
24 * mailbox channel provided by Broadcom SoC specific ring manager driver.
32 #include <linux/dma-mapping.h>
36 #include <linux/mailbox/brcm-message.h>
85 #define to_sba_request(tx) \ argument
86 container_of(tx, struct sba_request, tx)
113 struct dma_async_tx_descriptor tx; member
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/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Dmbox.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 # error "incorrect mailbox area sizes"
37 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
43 /* Mailbox directions */
70 u64 tx_start; /* Offset of Tx region in mbox memory */
72 u16 tx_size; /* Size of Tx region */
92 u16 next_msgoff; /* Offset of next msg within mailbox region */
127 /* Mailbox message types */
133 /* Generic mbox IDs (range 0x000 - 0x1FF) */ \
147 /* CGX mbox IDs (range 0x200 - 0x3FF) */ \
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/linux/drivers/net/ethernet/meta/fbnic/
H A Dfbnic_fw.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/dma-mapping.h>
53 for (desc_idx = FBNIC_IPC_MBX_DESC_LEN; --desc_idx;) { in fbnic_mbx_init_desc_ring()
65 /* Initialize lock to protect Tx ring */ in fbnic_mbx_init()
66 spin_lock_init(&fbd->fw_tx_lock); in fbnic_mbx_init()
68 /* Reinitialize mailbox memory */ in fbnic_mbx_init()
70 memset(&fbd->mbx[i], 0, sizeof(struct fbnic_fw_mbx)); in fbnic_mbx_init()
72 /* Do not auto-clear the FW mailbox interrupt, let SW clear it */ in fbnic_mbx_init()
85 struct fbnic_fw_mbx *mbx = &fbd->mbx[mbx_idx]; in fbnic_mbx_map_msg()
86 u8 tail = mbx->tail; in fbnic_mbx_map_msg()
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/linux/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_83xx_hw.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (c) 2009-2013 QLogic Corporation
38 #define QLC_83XX_MODULE_FIBRE_10GBASE_LRM 0x1 /* 10GBase-LRM */
39 #define QLC_83XX_MODULE_FIBRE_10GBASE_LR 0x2 /* 10GBase-LR */
40 #define QLC_83XX_MODULE_FIBRE_10GBASE_SR 0x3 /* 10GBase-SR */
50 #define QLC_83XX_MODULE_FIBRE_1000BASE_SX 0x7 /* 1000Base-SX */
51 #define QLC_83XX_MODULE_FIBRE_1000BASE_LX 0x8 /* 1000Base-LX */
52 #define QLC_83XX_MODULE_FIBRE_1000BASE_CX 0x9 /* 1000Base-CX */
53 #define QLC_83XX_MODULE_TP_1000BASE_T 0xa /* 1000Base-T*/
262 ahw->hw_ops = &qlcnic_83xx_hw_ops; in qlcnic_83xx_register_map()
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/linux/drivers/net/can/
H A Dat91_can.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * at91_can.c - CAN network driver for AT91 SoC CAN controller
6 * (C) 2008, 2009, 2010, 2011, 2023 by Marc Kleine-Budde <kernel@pengutronix.de>
29 #include <linux/can/rx-offload.h>
31 #define AT91_MB_MASK(i) ((1 << (i)) - 1)
48 /* Mailbox registers (0 <= i <= 15) */
106 /* Mailbox Modes */
202 return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \
210 return priv->devtype_data.rx_first; in get_mb_rx_first()
215 return priv->devtype_data.rx_last; in get_mb_rx_last()
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_type.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2023, Intel Corporation. */
35 ((((N) + (R) - 1) / (R)) * (R))); in ice_round_to_num()
41 /* debug masks - set these bits in hw->debug_mask to control output */
187 * order to clean the Tx scheduler as a part of the reset
214 /* NONE - used for undef/error */
271 /* Tx/Rx queues */
274 u16 num_txq; /* Number/Total Tx queues */
275 u16 txq_first_id; /* First queue ID for Tx queues */
277 /* MSI-X vectors */
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/linux/drivers/net/ethernet/intel/igb/
H A De1000_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
7 #define E1000_CTRL 0x00000 /* Device Control - RW */
8 #define E1000_STATUS 0x00008 /* Device Status - RO */
9 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
10 #define E1000_EERD 0x00014 /* EEPROM Read - RW */
11 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
12 #define E1000_MDIC 0x00020 /* MDI Control - RW */
13 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */
14 #define E1000_SCTL 0x00024 /* SerDes Control - RW */
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/linux/drivers/net/ethernet/marvell/octeon_ep/
H A Doctep_main.h1 /* SPDX-License-Identifier: GPL-2.0 */
51 ((iq__)->host_write_index - (iq__)->flush_index) & \
52 (iq__)->ring_size_mask; \
55 (iq_)->max_count - IQ_INSTR_PENDING(iq_); \
113 /* Octeon mailbox data */
130 /* Octeon device mailbox */
145 /* Tx/Rx queue vector per interrupt. */
254 /* Tx queues (IQ: Instruction Queue) */
257 /* Pointers to Octeon Tx queues */
278 /* IOq information of it's corresponding MSI-X interrupt. */
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/linux/drivers/net/can/rcar/
H A Drcar_can.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Renesas R-Car CAN device driver
32 /* Mailbox configuration:
33 * mailbox 60 - 63 - Rx FIFO mailboxes
34 * mailbox 56 - 59 - Tx FIFO mailboxes
35 * non-FIFO mailboxes are not used
37 #define RCAR_CAN_N_MBX 64 /* Number of mailboxes in non-FIFO mode */
38 #define RCAR_CAN_RX_FIFO_MBX 60 /* Mailbox - window to Rx FIFO */
39 #define RCAR_CAN_TX_FIFO_MBX 56 /* Mailbox - window to Tx FIFO */
42 /* Mailbox registers structure */
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/linux/drivers/thunderbolt/
H A Dnhi_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt driver - NHI registers
15 RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */
23 * struct ring_desc - TX/RX ring entry
25 * For TX set length/eof/sof.
44 * 12: descriptor count
53 * 12: descriptor count
69 * If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to
70 * the corresponding TX hop id.
79 * three bitfields: tx, rx, rx overflow
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/linux/drivers/net/ethernet/cavium/thunder/
H A Dnic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
35 /* NIC SRIOV VF count */
80 /* MSI-X interrupts */
98 * for reception it will not get dropped due to non-availability
114 * Since both pkt rx and tx notifications are done with same CQ,
235 /* CQE Tx errs */
266 int count; member
306 /* Queue count */
329 /* mutex to protect VF's mailbox contents from concurrent access */
371 /* MSI-X */
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/linux/drivers/net/ethernet/marvell/octeon_ep_vf/
H A Doctep_vf_cn9k.c1 // SPDX-License-Identifier: GPL-2.0
19 struct device *dev = &oct->pdev->dev; in cn93_vf_dump_q_regs()
21 dev_info(dev, "IQ-%d register dump\n", qno); in cn93_vf_dump_q_regs()
50 dev_info(dev, "OQ-%d register dump\n", qno); in cn93_vf_dump_q_regs()
80 /* Reset Hardware Tx queue */
85 dev_dbg(&oct->pdev->dev, "Reset VF IQ-%d\n", q_no); in cn93_vf_reset_iq()
87 /* Disable the Tx/Instruction Ring */ in cn93_vf_reset_iq()
113 /* Clear count CSRs */ in cn93_vf_reset_oq()
121 /* Reset all hardware Tx/Rx queues */
124 struct pci_dev *pdev = oct->pdev; in octep_vf_reset_io_queues_cn93()
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