Lines Matching +full:tx +full:- +full:mailbox +full:- +full:count
1 // SPDX-License-Identifier: GPL-2.0-only
7 * Broadcom PDC Mailbox Driver
9 * offload engines. For example, the PDC driver works with both SPU-M and SPU2
13 * The PDC driver registers with the Linux mailbox framework as a mailbox
15 * a mailbox channel. The PDC driver uses interrupts to determine when data
25 * descriptors from the tx and rx ring, thus processing one response at a time.
41 #include <linux/mailbox/brcm-message.h>
43 #include <linux/dma-direction.h>
44 #include <linux/dma-mapping.h>
55 * Minimum number of ring descriptor entries that must be free to tell mailbox
73 #define PREVTXD(i, max_mask) TXD((i) - 1, (max_mask))
75 #define PREVRXD(i, max_mask) RXD((i) - 1, (max_mask))
76 #define NTXDACTIVE(h, t, max_mask) TXD((t) - (h), (max_mask))
77 #define NRXDACTIVE(h, t, max_mask) RXD((t) - (h), (max_mask))
89 * Interrupt mask and status definitions. Enable interrupts for tx and rx on
115 * 11 - PtyChkDisable - parity check is disabled
116 * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory
120 /* Bit in tx control reg to enable tx channel */
125 * 7:1 - RcvOffset - size in bytes of status region at start of rx frame buf
126 * 9 - SepRxHdrDescEn - place start of new frames only in descriptors
128 * 10 - OflowContinue - on rx FIFO overflow, clear rx fifo, discard all
131 * 11 - PtyChkDisable - parity check is disabled
132 * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory
139 #define CRYPTO_D64_RS0_CD_MASK ((PDC_RING_ENTRIES * RING_ENTRY_SIZE) - 1)
164 u32 ctrl2; /* buffer count and address extension */
173 u32 addrlow; /* descriptor ring base address low 32-bits */
188 struct dma64_regs dmaxmt; /* dma tx */
236 u32 PAD[11]; /* 0x1b4-1dc */
243 struct dma64 dmaregs[PDC_NUM_DMA_RINGS]; /* 0x0200 - 0x2fc */
285 * Each PDC instance has a mailbox controller. PDC receives request
287 * mailbox framework.
313 * The base virtual address of DMA tx/rx descriptor rings. Corresponding
321 struct dma64_regs *txregs_64; /* dma tx engine registers */
328 struct dma64dd *txd_64; /* tx descriptor ring */
332 u32 ntxd; /* # tx descriptors */
335 u32 ntxpost; /* max number of tx buffers that can be posted */
338 * Index of next tx descriptor to reclaim. That is, the descriptor
339 * index of the oldest tx buffer for which the host has yet to process
347 * the rxin_numd count for a message. Updated to rxout when the host
352 /* Index of next tx descriptor to post. */
356 * Number of tx descriptors associated with the message that starts
357 * at this tx descriptor index.
370 * the rxin_numd count for a message. Updated to rxout when the host
397 u32 last_tx_not_done; /* too few tx descriptors to indicate done */
398 u32 tx_ring_full; /* unable to accept msg because tx ring full */
400 u32 txnobuf; /* unable to create tx descriptor */
402 u32 rx_oflow; /* count of rx overflows */
404 /* hardware type - FA2 or PDC/MDE */
421 size_t count, loff_t *offp) in pdc_debugfs_read() argument
431 return -ENOMEM; in pdc_debugfs_read()
433 pdcs = filp->private_data; in pdc_debugfs_read()
435 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
436 "SPU %u stats:\n", pdcs->pdc_idx); in pdc_debugfs_read()
437 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
439 pdcs->pdc_requests); in pdc_debugfs_read()
440 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
442 pdcs->pdc_replies); in pdc_debugfs_read()
443 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
444 "Tx not done.....................%u\n", in pdc_debugfs_read()
445 pdcs->last_tx_not_done); in pdc_debugfs_read()
446 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
447 "Tx ring full....................%u\n", in pdc_debugfs_read()
448 pdcs->tx_ring_full); in pdc_debugfs_read()
449 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
451 pdcs->rx_ring_full); in pdc_debugfs_read()
452 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
453 "Tx desc write fail. Ring full...%u\n", in pdc_debugfs_read()
454 pdcs->txnobuf); in pdc_debugfs_read()
455 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
457 pdcs->rxnobuf); in pdc_debugfs_read()
458 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
460 pdcs->rx_oflow); in pdc_debugfs_read()
461 out_offset += scnprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
463 NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, in pdc_debugfs_read()
464 pdcs->nrxpost)); in pdc_debugfs_read()
469 ret = simple_read_from_buffer(ubuf, count, offp, buf, out_offset); in pdc_debugfs_read()
481 * pdc_setup_debugfs() - Create the debug FS directories. If the top-level
493 snprintf(spu_stats_name, 16, "pdc%d_stats", pdcs->pdc_idx); in pdc_setup_debugfs()
509 * pdc_build_rxd() - Build DMA descriptor to receive SPU result.
519 struct device *dev = &pdcs->pdev->dev; in pdc_build_rxd()
520 struct dma64dd *rxd = &pdcs->rxd_64[pdcs->rxout]; in pdc_build_rxd()
524 pdcs->pdc_idx, pdcs->rxout, buf_len, flags); in pdc_build_rxd()
526 rxd->addrlow = cpu_to_le32(lower_32_bits(dma_addr)); in pdc_build_rxd()
527 rxd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr)); in pdc_build_rxd()
528 rxd->ctrl1 = cpu_to_le32(flags); in pdc_build_rxd()
529 rxd->ctrl2 = cpu_to_le32(buf_len); in pdc_build_rxd()
532 pdcs->rxout = NEXTRXD(pdcs->rxout, pdcs->nrxpost); in pdc_build_rxd()
536 * pdc_build_txd() - Build a DMA descriptor to transmit a SPU request to
540 * @buf_len: Length of tx buffer, in bytes
547 struct device *dev = &pdcs->pdev->dev; in pdc_build_txd()
548 struct dma64dd *txd = &pdcs->txd_64[pdcs->txout]; in pdc_build_txd()
551 "Writing tx descriptor for PDC %u at index %u with length %u, flags %#x\n", in pdc_build_txd()
552 pdcs->pdc_idx, pdcs->txout, buf_len, flags); in pdc_build_txd()
554 txd->addrlow = cpu_to_le32(lower_32_bits(dma_addr)); in pdc_build_txd()
555 txd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr)); in pdc_build_txd()
556 txd->ctrl1 = cpu_to_le32(flags); in pdc_build_txd()
557 txd->ctrl2 = cpu_to_le32(buf_len); in pdc_build_txd()
560 pdcs->txout = NEXTTXD(pdcs->txout, pdcs->ntxpost); in pdc_build_txd()
564 * pdc_receive_one() - Receive a response message from a given SPU.
571 * -EAGAIN indicates that no response message is available
572 * -EIO an error occurred
577 struct device *dev = &pdcs->pdev->dev; in pdc_receive_one()
589 mbc = &pdcs->mbc; in pdc_receive_one()
590 chan = &mbc->chans[0]; in pdc_receive_one()
598 frags_rdy = NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, pdcs->nrxpost); in pdc_receive_one()
600 (frags_rdy < pdcs->rx_ctx[pdcs->rxin].rxin_numd)) in pdc_receive_one()
602 return -EAGAIN; in pdc_receive_one()
604 num_frags = pdcs->txin_numd[pdcs->txin]; in pdc_receive_one()
607 dma_unmap_sg(dev, pdcs->src_sg[pdcs->txin], in pdc_receive_one()
608 sg_nents(pdcs->src_sg[pdcs->txin]), DMA_TO_DEVICE); in pdc_receive_one()
610 pdcs->txin = (pdcs->txin + num_frags) & pdcs->ntxpost; in pdc_receive_one()
612 dev_dbg(dev, "PDC %u reclaimed %d tx descriptors", in pdc_receive_one()
613 pdcs->pdc_idx, num_frags); in pdc_receive_one()
615 rx_idx = pdcs->rxin; in pdc_receive_one()
616 rx_ctx = &pdcs->rx_ctx[rx_idx]; in pdc_receive_one()
617 num_frags = rx_ctx->rxin_numd; in pdc_receive_one()
619 mssg.ctx = rx_ctx->rxp_ctx; in pdc_receive_one()
620 rx_ctx->rxp_ctx = NULL; in pdc_receive_one()
621 resp_hdr = rx_ctx->resp_hdr; in pdc_receive_one()
622 resp_hdr_daddr = rx_ctx->resp_hdr_daddr; in pdc_receive_one()
623 dma_unmap_sg(dev, rx_ctx->dst_sg, sg_nents(rx_ctx->dst_sg), in pdc_receive_one()
626 pdcs->rxin = (pdcs->rxin + num_frags) & pdcs->nrxpost; in pdc_receive_one()
629 pdcs->pdc_idx, num_frags); in pdc_receive_one()
633 pdcs->pdc_idx, pdcs->txin, pdcs->txout, pdcs->rxin, in pdc_receive_one()
634 pdcs->rxout, pdcs->last_rx_curr); in pdc_receive_one()
636 if (pdcs->pdc_resp_hdr_len == PDC_SPUM_RESP_HDR_LEN) { in pdc_receive_one()
638 * For SPU-M, get length of response msg and rx overflow status. in pdc_receive_one()
648 pdcs->rx_oflow++; in pdc_receive_one()
652 return -EIO; in pdc_receive_one()
656 dma_pool_free(pdcs->rx_buf_pool, resp_hdr, resp_hdr_daddr); in pdc_receive_one()
660 pdcs->pdc_replies++; in pdc_receive_one()
665 * pdc_receive() - Process as many responses as are available in the rx ring.
677 pdcs->last_rx_curr = in pdc_receive()
678 (ioread32((const void __iomem *)&pdcs->rxregs_64->status0) & in pdc_receive()
690 * pdc_tx_list_sg_add() - Add the buffers in a scatterlist to the transmit
713 u32 desc_w = 0; /* Number of tx descriptors written */ in pdc_tx_list_sg_add()
719 /* check whether enough tx descriptors are available */ in pdc_tx_list_sg_add()
720 tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout, in pdc_tx_list_sg_add()
721 pdcs->ntxpost); in pdc_tx_list_sg_add()
723 pdcs->txnobuf++; in pdc_tx_list_sg_add()
724 return -ENOSPC; in pdc_tx_list_sg_add()
727 /* build tx descriptors */ in pdc_tx_list_sg_add()
728 if (pdcs->tx_msg_start == pdcs->txout) { in pdc_tx_list_sg_add()
730 pdcs->txin_numd[pdcs->tx_msg_start] = 0; in pdc_tx_list_sg_add()
731 pdcs->src_sg[pdcs->txout] = sg; in pdc_tx_list_sg_add()
736 if (unlikely(pdcs->txout == (pdcs->ntxd - 1))) in pdc_tx_list_sg_add()
751 bufcnt -= PDC_DMA_BUF_MAX; in pdc_tx_list_sg_add()
753 if (unlikely(pdcs->txout == (pdcs->ntxd - 1))) in pdc_tx_list_sg_add()
767 pdcs->txin_numd[pdcs->tx_msg_start] += desc_w; in pdc_tx_list_sg_add()
773 * pdc_tx_list_final() - Initiate DMA transfer of last frame written to tx
777 * Sets the index of the last descriptor written in both the rx and tx ring.
788 iowrite32(pdcs->rxout << 4, &pdcs->rxregs_64->ptr); in pdc_tx_list_final()
789 iowrite32(pdcs->txout << 4, &pdcs->txregs_64->ptr); in pdc_tx_list_final()
790 pdcs->pdc_requests++; in pdc_tx_list_final()
796 * pdc_rx_list_init() - Start a new receive descriptor list for a given PDC.
799 * mailbox client
803 * response. For example, with SPU-M, the metadata is a 32-byte DMA header and
804 * an 8-byte BCM header. Moves the msg_start descriptor indexes for both tx and
820 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, in pdc_rx_list_init()
821 pdcs->nrxpost); in pdc_rx_list_init()
823 pdcs->rxnobuf++; in pdc_rx_list_init()
824 return -ENOSPC; in pdc_rx_list_init()
828 vaddr = dma_pool_zalloc(pdcs->rx_buf_pool, GFP_ATOMIC, &daddr); in pdc_rx_list_init()
830 return -ENOMEM; in pdc_rx_list_init()
833 * Update msg_start indexes for both tx and rx to indicate the start in pdc_rx_list_init()
837 pdcs->rx_msg_start = pdcs->rxout; in pdc_rx_list_init()
838 pdcs->tx_msg_start = pdcs->txout; in pdc_rx_list_init()
842 pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd = 1; in pdc_rx_list_init()
844 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) in pdc_rx_list_init()
847 rx_ctx = &pdcs->rx_ctx[pdcs->rxout]; in pdc_rx_list_init()
848 rx_ctx->rxp_ctx = ctx; in pdc_rx_list_init()
849 rx_ctx->dst_sg = dst_sg; in pdc_rx_list_init()
850 rx_ctx->resp_hdr = vaddr; in pdc_rx_list_init()
851 rx_ctx->resp_hdr_daddr = daddr; in pdc_rx_list_init()
852 pdc_build_rxd(pdcs, daddr, pdcs->pdc_resp_hdr_len, flags); in pdc_rx_list_init()
857 * pdc_rx_list_sg_add() - Add the buffers in a scatterlist to the receive
880 u32 desc_w = 0; /* Number of tx descriptors written */ in pdc_rx_list_sg_add()
886 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, in pdc_rx_list_sg_add()
887 pdcs->nrxpost); in pdc_rx_list_sg_add()
889 pdcs->rxnobuf++; in pdc_rx_list_sg_add()
890 return -ENOSPC; in pdc_rx_list_sg_add()
894 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) in pdc_rx_list_sg_add()
908 bufcnt -= PDC_DMA_BUF_MAX; in pdc_rx_list_sg_add()
910 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) in pdc_rx_list_sg_add()
919 pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd += desc_w; in pdc_rx_list_sg_add()
925 * pdc_irq_handler() - Interrupt handler called in interrupt context.
940 u32 intstatus = ioread32(pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET); in pdc_irq_handler()
946 iowrite32(0, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); in pdc_irq_handler()
949 iowrite32(intstatus, pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET); in pdc_irq_handler()
952 queue_work(system_bh_wq, &pdcs->rx_work); in pdc_irq_handler()
957 * pdc_work_cb() - Work callback that runs the deferred processing after
968 iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); in pdc_work_cb()
972 * pdc_ring_init() - Allocate DMA rings and initialize constant fields of
985 struct device *dev = &pdcs->pdev->dev; in pdc_ring_init()
986 struct pdc_ring_alloc tx; in pdc_ring_init() local
989 /* Allocate tx ring */ in pdc_ring_init()
990 tx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &tx.dmabase); in pdc_ring_init()
991 if (unlikely(!tx.vbase)) { in pdc_ring_init()
992 err = -ENOMEM; in pdc_ring_init()
997 rx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &rx.dmabase); in pdc_ring_init()
999 err = -ENOMEM; in pdc_ring_init()
1003 dev_dbg(dev, " - base DMA addr of tx ring %pad", &tx.dmabase); in pdc_ring_init()
1004 dev_dbg(dev, " - base virtual addr of tx ring %p", tx.vbase); in pdc_ring_init()
1005 dev_dbg(dev, " - base DMA addr of rx ring %pad", &rx.dmabase); in pdc_ring_init()
1006 dev_dbg(dev, " - base virtual addr of rx ring %p", rx.vbase); in pdc_ring_init()
1008 memcpy(&pdcs->tx_ring_alloc, &tx, sizeof(tx)); in pdc_ring_init()
1009 memcpy(&pdcs->rx_ring_alloc, &rx, sizeof(rx)); in pdc_ring_init()
1011 pdcs->rxin = 0; in pdc_ring_init()
1012 pdcs->rx_msg_start = 0; in pdc_ring_init()
1013 pdcs->last_rx_curr = 0; in pdc_ring_init()
1014 pdcs->rxout = 0; in pdc_ring_init()
1015 pdcs->txin = 0; in pdc_ring_init()
1016 pdcs->tx_msg_start = 0; in pdc_ring_init()
1017 pdcs->txout = 0; in pdc_ring_init()
1020 pdcs->txd_64 = (struct dma64dd *)pdcs->tx_ring_alloc.vbase; in pdc_ring_init()
1021 pdcs->rxd_64 = (struct dma64dd *)pdcs->rx_ring_alloc.vbase; in pdc_ring_init()
1024 dma_reg = &pdcs->regs->dmaregs[ringset]; in pdc_ring_init()
1026 /* But first disable DMA and set curptr to 0 for both TX & RX */ in pdc_ring_init()
1027 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); in pdc_ring_init()
1028 iowrite32((PDC_RX_CTL + (pdcs->rx_status_len << 1)), in pdc_ring_init()
1029 &dma_reg->dmarcv.control); in pdc_ring_init()
1030 iowrite32(0, &dma_reg->dmaxmt.ptr); in pdc_ring_init()
1031 iowrite32(0, &dma_reg->dmarcv.ptr); in pdc_ring_init()
1034 iowrite32(lower_32_bits(pdcs->tx_ring_alloc.dmabase), in pdc_ring_init()
1035 &dma_reg->dmaxmt.addrlow); in pdc_ring_init()
1036 iowrite32(upper_32_bits(pdcs->tx_ring_alloc.dmabase), in pdc_ring_init()
1037 &dma_reg->dmaxmt.addrhigh); in pdc_ring_init()
1039 iowrite32(lower_32_bits(pdcs->rx_ring_alloc.dmabase), in pdc_ring_init()
1040 &dma_reg->dmarcv.addrlow); in pdc_ring_init()
1041 iowrite32(upper_32_bits(pdcs->rx_ring_alloc.dmabase), in pdc_ring_init()
1042 &dma_reg->dmarcv.addrhigh); in pdc_ring_init()
1044 /* Re-enable DMA */ in pdc_ring_init()
1045 iowrite32(PDC_TX_CTL | PDC_TX_ENABLE, &dma_reg->dmaxmt.control); in pdc_ring_init()
1046 iowrite32((PDC_RX_CTL | PDC_RX_ENABLE | (pdcs->rx_status_len << 1)), in pdc_ring_init()
1047 &dma_reg->dmarcv.control); in pdc_ring_init()
1051 /* Every tx descriptor can be used for start of frame. */ in pdc_ring_init()
1052 if (i != pdcs->ntxpost) { in pdc_ring_init()
1054 &pdcs->txd_64[i].ctrl1); in pdc_ring_init()
1058 D64_CTRL1_EOT, &pdcs->txd_64[i].ctrl1); in pdc_ring_init()
1062 if (i != pdcs->nrxpost) { in pdc_ring_init()
1064 &pdcs->rxd_64[i].ctrl1); in pdc_ring_init()
1068 &pdcs->rxd_64[i].ctrl1); in pdc_ring_init()
1074 dma_pool_free(pdcs->ring_pool, tx.vbase, tx.dmabase); in pdc_ring_init()
1081 if (pdcs->tx_ring_alloc.vbase) { in pdc_ring_free()
1082 dma_pool_free(pdcs->ring_pool, pdcs->tx_ring_alloc.vbase, in pdc_ring_free()
1083 pdcs->tx_ring_alloc.dmabase); in pdc_ring_free()
1084 pdcs->tx_ring_alloc.vbase = NULL; in pdc_ring_free()
1087 if (pdcs->rx_ring_alloc.vbase) { in pdc_ring_free()
1088 dma_pool_free(pdcs->ring_pool, pdcs->rx_ring_alloc.vbase, in pdc_ring_free()
1089 pdcs->rx_ring_alloc.dmabase); in pdc_ring_free()
1090 pdcs->rx_ring_alloc.vbase = NULL; in pdc_ring_free()
1095 * pdc_desc_count() - Count the number of DMA descriptors that will be required
1105 cnt += ((sg->length / PDC_DMA_BUF_MAX) + 1); in pdc_desc_count()
1112 * pdc_rings_full() - Check whether the tx ring has room for tx_cnt descriptors
1115 * @tx_cnt: The number of descriptors required in the tx ring
1127 /* Check if the tx and rx rings are likely to have enough space */ in pdc_rings_full()
1128 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, in pdc_rings_full()
1129 pdcs->nrxpost); in pdc_rings_full()
1131 pdcs->rx_ring_full++; in pdc_rings_full()
1136 tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout, in pdc_rings_full()
1137 pdcs->ntxpost); in pdc_rings_full()
1139 pdcs->tx_ring_full++; in pdc_rings_full()
1147 * pdc_last_tx_done() - If both the tx and rx rings have at least
1148 * PDC_RING_SPACE_MIN descriptors available, then indicate that the mailbox
1150 * @chan: mailbox channel to check
1155 struct pdc_state *pdcs = chan->con_priv; in pdc_last_tx_done()
1160 pdcs->last_tx_not_done++; in pdc_last_tx_done()
1169 * pdc_send_data() - mailbox send_data function
1170 * @chan: The mailbox channel on which the data is sent. The channel
1172 * @data: The mailbox message to be sent. The message must be a
1175 * This function is registered as the send_data function for the mailbox
1176 * controller. From the destination scatterlist in the mailbox message, it
1178 * scatterlist, it creates a sequence of transmit descriptors in the tx ring.
1179 * After creating the descriptors, it writes the rx ptr and tx ptr registers to
1183 * the mailbox message.
1186 * -ENOTSUPP if the mailbox message is a type this driver does not
1192 struct pdc_state *pdcs = chan->con_priv; in pdc_send_data()
1193 struct device *dev = &pdcs->pdev->dev; in pdc_send_data()
1202 if (unlikely(mssg->type != BRCM_MESSAGE_SPU)) in pdc_send_data()
1203 return -ENOTSUPP; in pdc_send_data()
1205 src_nent = sg_nents(mssg->spu.src); in pdc_send_data()
1207 nent = dma_map_sg(dev, mssg->spu.src, src_nent, DMA_TO_DEVICE); in pdc_send_data()
1209 return -EIO; in pdc_send_data()
1212 dst_nent = sg_nents(mssg->spu.dst); in pdc_send_data()
1214 nent = dma_map_sg(dev, mssg->spu.dst, dst_nent, in pdc_send_data()
1217 dma_unmap_sg(dev, mssg->spu.src, src_nent, in pdc_send_data()
1219 return -EIO; in pdc_send_data()
1224 * Check if the tx and rx rings have enough space. Do this prior to in pdc_send_data()
1225 * writing any tx or rx descriptors. Need to ensure that we do not write in pdc_send_data()
1227 * corresponding tx descriptors don't fit. Note that we want this check in pdc_send_data()
1229 * thread getting in. The channel spin lock in the mailbox framework in pdc_send_data()
1232 tx_desc_req = pdc_desc_count(mssg->spu.src); in pdc_send_data()
1233 rx_desc_req = pdc_desc_count(mssg->spu.dst); in pdc_send_data()
1235 return -ENOSPC; in pdc_send_data()
1238 err = pdc_rx_list_init(pdcs, mssg->spu.dst, mssg->ctx); in pdc_send_data()
1239 err |= pdc_rx_list_sg_add(pdcs, mssg->spu.dst); in pdc_send_data()
1241 /* Create tx descriptors to submit SPU request */ in pdc_send_data()
1242 err |= pdc_tx_list_sg_add(pdcs, mssg->spu.src); in pdc_send_data()
1246 dev_err(&pdcs->pdev->dev, in pdc_send_data()
1254 return pdc_ring_init(chan->con_priv, PDC_RINGSET); in pdc_startup()
1259 struct pdc_state *pdcs = chan->con_priv; in pdc_shutdown()
1264 dev_dbg(&pdcs->pdev->dev, in pdc_shutdown()
1265 "Shutdown mailbox channel for PDC %u", pdcs->pdc_idx); in pdc_shutdown()
1270 * pdc_hw_init() - Use the given initialization parameters to initialize the
1282 pdev = pdcs->pdev; in pdc_hw_init()
1283 dev = &pdev->dev; in pdc_hw_init()
1285 dev_dbg(dev, "PDC %u initial values:", pdcs->pdc_idx); in pdc_hw_init()
1288 dev_dbg(dev, " - base virtual addr of hw regs %p", in pdc_hw_init()
1289 pdcs->pdc_reg_vbase); in pdc_hw_init()
1292 pdcs->regs = (struct pdc_regs *)pdcs->pdc_reg_vbase; in pdc_hw_init()
1293 pdcs->txregs_64 = (struct dma64_regs *) in pdc_hw_init()
1294 (((u8 *)pdcs->pdc_reg_vbase) + in pdc_hw_init()
1296 pdcs->rxregs_64 = (struct dma64_regs *) in pdc_hw_init()
1297 (((u8 *)pdcs->pdc_reg_vbase) + in pdc_hw_init()
1300 pdcs->ntxd = PDC_RING_ENTRIES; in pdc_hw_init()
1301 pdcs->nrxd = PDC_RING_ENTRIES; in pdc_hw_init()
1302 pdcs->ntxpost = PDC_RING_ENTRIES - 1; in pdc_hw_init()
1303 pdcs->nrxpost = PDC_RING_ENTRIES - 1; in pdc_hw_init()
1304 iowrite32(0, &pdcs->regs->intmask); in pdc_hw_init()
1306 dma_reg = &pdcs->regs->dmaregs[ringset]; in pdc_hw_init()
1309 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); in pdc_hw_init()
1311 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1), in pdc_hw_init()
1312 &dma_reg->dmarcv.control); in pdc_hw_init()
1315 iowrite32(0, &dma_reg->dmaxmt.ptr); in pdc_hw_init()
1316 iowrite32(0, &dma_reg->dmarcv.ptr); in pdc_hw_init()
1318 if (pdcs->pdc_resp_hdr_len == PDC_SPU2_RESP_HDR_LEN) in pdc_hw_init()
1320 pdcs->pdc_reg_vbase + PDC_CKSUM_CTRL_OFFSET); in pdc_hw_init()
1324 * pdc_hw_disable() - Disable the tx and rx control in the hw.
1332 dma_reg = &pdcs->regs->dmaregs[PDC_RINGSET]; in pdc_hw_disable()
1333 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); in pdc_hw_disable()
1334 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1), in pdc_hw_disable()
1335 &dma_reg->dmarcv.control); in pdc_hw_disable()
1339 * pdc_rx_buf_pool_create() - Pool of receive buffers used to catch the metadata
1343 * The metadata is not returned to the mailbox client. So the PDC driver
1347 * -ENOMEM if pool creation fails
1354 pdev = pdcs->pdev; in pdc_rx_buf_pool_create()
1355 dev = &pdev->dev; in pdc_rx_buf_pool_create()
1357 pdcs->pdc_resp_hdr_len = pdcs->rx_status_len; in pdc_rx_buf_pool_create()
1358 if (pdcs->use_bcm_hdr) in pdc_rx_buf_pool_create()
1359 pdcs->pdc_resp_hdr_len += BCM_HDR_LEN; in pdc_rx_buf_pool_create()
1361 pdcs->rx_buf_pool = dma_pool_create("pdc rx bufs", dev, in pdc_rx_buf_pool_create()
1362 pdcs->pdc_resp_hdr_len, in pdc_rx_buf_pool_create()
1364 if (!pdcs->rx_buf_pool) in pdc_rx_buf_pool_create()
1365 return -ENOMEM; in pdc_rx_buf_pool_create()
1371 * pdc_interrupts_init() - Initialize the interrupt configuration for a PDC and
1377 * Set the lazy interrupt frame count to generate an interrupt for just one pkt.
1384 struct platform_device *pdev = pdcs->pdev; in pdc_interrupts_init()
1385 struct device *dev = &pdev->dev; in pdc_interrupts_init()
1386 struct device_node *dn = pdev->dev.of_node; in pdc_interrupts_init()
1390 iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); in pdc_interrupts_init()
1392 if (pdcs->hw_type == FA_HW) in pdc_interrupts_init()
1393 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase + in pdc_interrupts_init()
1396 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase + in pdc_interrupts_init()
1400 pdcs->pdc_irq = irq_of_parse_and_map(dn, 0); in pdc_interrupts_init()
1402 dev_name(dev), pdcs->pdc_irq, pdcs); in pdc_interrupts_init()
1404 err = devm_request_irq(dev, pdcs->pdc_irq, pdc_irq_handler, 0, in pdc_interrupts_init()
1408 pdcs->pdc_irq, err); in pdc_interrupts_init()
1422 * pdc_mb_init() - Initialize the mailbox controller.
1425 * Each PDC is a mailbox controller. Each ringset is a mailbox channel. Kernel
1427 * complete interrupt to determine when a mailbox message has successfully been
1435 struct device *dev = &pdcs->pdev->dev; in pdc_mb_init()
1440 mbc = &pdcs->mbc; in pdc_mb_init()
1441 mbc->dev = dev; in pdc_mb_init()
1442 mbc->ops = &pdc_mbox_chan_ops; in pdc_mb_init()
1443 mbc->num_chans = 1; in pdc_mb_init()
1444 mbc->chans = devm_kcalloc(dev, mbc->num_chans, sizeof(*mbc->chans), in pdc_mb_init()
1446 if (!mbc->chans) in pdc_mb_init()
1447 return -ENOMEM; in pdc_mb_init()
1449 mbc->txdone_irq = false; in pdc_mb_init()
1450 mbc->txdone_poll = true; in pdc_mb_init()
1451 mbc->txpoll_period = 1; in pdc_mb_init()
1452 for (chan_index = 0; chan_index < mbc->num_chans; chan_index++) in pdc_mb_init()
1453 mbc->chans[chan_index].con_priv = pdcs; in pdc_mb_init()
1455 /* Register mailbox controller */ in pdc_mb_init()
1459 "Failed to register PDC mailbox controller. Error %d.", in pdc_mb_init()
1471 {.compatible = "brcm,iproc-pdc-mbox", .data = &pdc_hw},
1472 {.compatible = "brcm,iproc-fa2-mbox", .data = &fa_hw},
1478 * pdc_dt_read() - Read application-specific data from device tree.
1483 * Reads whether transmit and received frames should be preceded by an 8-byte
1487 * -ENODEV if device not available
1491 struct device *dev = &pdev->dev; in pdc_dt_read()
1492 struct device_node *dn = pdev->dev.of_node; in pdc_dt_read()
1496 err = of_property_read_u32(dn, "brcm,rx-status-len", in pdc_dt_read()
1497 &pdcs->rx_status_len); in pdc_dt_read()
1503 pdcs->use_bcm_hdr = of_property_read_bool(dn, "brcm,use-bcm-hdr"); in pdc_dt_read()
1505 pdcs->hw_type = PDC_HW; in pdc_dt_read()
1509 pdcs->hw_type = *hw_type; in pdc_dt_read()
1515 * pdc_probe() - Probe function for PDC driver.
1519 * Allocate and initialize tx and rx DMA rings.
1520 * Initialize a mailbox controller for each PDC.
1528 struct device *dev = &pdev->dev; in pdc_probe()
1535 err = -ENOMEM; in pdc_probe()
1539 pdcs->pdev = pdev; in pdc_probe()
1541 pdcs->pdc_idx = pdcg.num_spu; in pdc_probe()
1550 /* Create DMA pool for tx ring */ in pdc_probe()
1551 pdcs->ring_pool = dma_pool_create("pdc rings", dev, PDC_RING_SIZE, in pdc_probe()
1553 if (!pdcs->ring_pool) { in pdc_probe()
1554 err = -ENOMEM; in pdc_probe()
1562 pdcs->pdc_reg_vbase = devm_platform_get_and_ioremap_resource(pdev, 0, &pdc_regs); in pdc_probe()
1563 if (IS_ERR(pdcs->pdc_reg_vbase)) { in pdc_probe()
1564 err = PTR_ERR(pdcs->pdc_reg_vbase); in pdc_probe()
1568 &pdc_regs->start, &pdc_regs->end); in pdc_probe()
1578 INIT_WORK(&pdcs->rx_work, pdc_work_cb); in pdc_probe()
1584 /* Initialize mailbox controller */ in pdc_probe()
1595 cancel_work_sync(&pdcs->rx_work); in pdc_probe()
1596 dma_pool_destroy(pdcs->rx_buf_pool); in pdc_probe()
1599 dma_pool_destroy(pdcs->ring_pool); in pdc_probe()
1611 cancel_work_sync(&pdcs->rx_work); in pdc_remove()
1615 dma_pool_destroy(pdcs->rx_buf_pool); in pdc_remove()
1616 dma_pool_destroy(pdcs->ring_pool); in pdc_remove()
1623 .name = "brcm-iproc-pdc-mbox",
1630 MODULE_DESCRIPTION("Broadcom PDC mailbox driver");