1 // SPDX-License-Identifier: GPL-2.0
2 /* Marvell Octeon EP (EndPoint) Ethernet Driver
3 *
4 * Copyright (C) 2020 Marvell.
5 *
6 */
7
8 #include <linux/pci.h>
9 #include <linux/netdevice.h>
10 #include <linux/etherdevice.h>
11
12 #include "octep_config.h"
13 #include "octep_main.h"
14 #include "octep_regs_cn9k_pf.h"
15
16 #define CTRL_MBOX_MAX_PF 128
17 #define CTRL_MBOX_SZ ((size_t)(0x400000 / CTRL_MBOX_MAX_PF))
18
19 /* Names of Hardware non-queue generic interrupts */
20 static char *cn93_non_ioq_msix_names[] = {
21 "epf_ire_rint",
22 "epf_ore_rint",
23 "epf_vfire_rint0",
24 "epf_vfire_rint1",
25 "epf_vfore_rint0",
26 "epf_vfore_rint1",
27 "epf_mbox_rint0",
28 "epf_mbox_rint1",
29 "epf_oei_rint",
30 "epf_dma_rint",
31 "epf_dma_vf_rint0",
32 "epf_dma_vf_rint1",
33 "epf_pp_vf_rint0",
34 "epf_pp_vf_rint1",
35 "epf_misc_rint",
36 "epf_rsvd",
37 };
38
39 /* Dump useful hardware CSRs for debug purpose */
cn93_dump_regs(struct octep_device * oct,int qno)40 static void cn93_dump_regs(struct octep_device *oct, int qno)
41 {
42 struct device *dev = &oct->pdev->dev;
43
44 dev_info(dev, "IQ-%d register dump\n", qno);
45 dev_info(dev, "R[%d]_IN_INSTR_DBELL[0x%llx]: 0x%016llx\n",
46 qno, CN93_SDP_R_IN_INSTR_DBELL(qno),
47 octep_read_csr64(oct, CN93_SDP_R_IN_INSTR_DBELL(qno)));
48 dev_info(dev, "R[%d]_IN_CONTROL[0x%llx]: 0x%016llx\n",
49 qno, CN93_SDP_R_IN_CONTROL(qno),
50 octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(qno)));
51 dev_info(dev, "R[%d]_IN_ENABLE[0x%llx]: 0x%016llx\n",
52 qno, CN93_SDP_R_IN_ENABLE(qno),
53 octep_read_csr64(oct, CN93_SDP_R_IN_ENABLE(qno)));
54 dev_info(dev, "R[%d]_IN_INSTR_BADDR[0x%llx]: 0x%016llx\n",
55 qno, CN93_SDP_R_IN_INSTR_BADDR(qno),
56 octep_read_csr64(oct, CN93_SDP_R_IN_INSTR_BADDR(qno)));
57 dev_info(dev, "R[%d]_IN_INSTR_RSIZE[0x%llx]: 0x%016llx\n",
58 qno, CN93_SDP_R_IN_INSTR_RSIZE(qno),
59 octep_read_csr64(oct, CN93_SDP_R_IN_INSTR_RSIZE(qno)));
60 dev_info(dev, "R[%d]_IN_CNTS[0x%llx]: 0x%016llx\n",
61 qno, CN93_SDP_R_IN_CNTS(qno),
62 octep_read_csr64(oct, CN93_SDP_R_IN_CNTS(qno)));
63 dev_info(dev, "R[%d]_IN_INT_LEVELS[0x%llx]: 0x%016llx\n",
64 qno, CN93_SDP_R_IN_INT_LEVELS(qno),
65 octep_read_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(qno)));
66 dev_info(dev, "R[%d]_IN_PKT_CNT[0x%llx]: 0x%016llx\n",
67 qno, CN93_SDP_R_IN_PKT_CNT(qno),
68 octep_read_csr64(oct, CN93_SDP_R_IN_PKT_CNT(qno)));
69 dev_info(dev, "R[%d]_IN_BYTE_CNT[0x%llx]: 0x%016llx\n",
70 qno, CN93_SDP_R_IN_BYTE_CNT(qno),
71 octep_read_csr64(oct, CN93_SDP_R_IN_BYTE_CNT(qno)));
72
73 dev_info(dev, "OQ-%d register dump\n", qno);
74 dev_info(dev, "R[%d]_OUT_SLIST_DBELL[0x%llx]: 0x%016llx\n",
75 qno, CN93_SDP_R_OUT_SLIST_DBELL(qno),
76 octep_read_csr64(oct, CN93_SDP_R_OUT_SLIST_DBELL(qno)));
77 dev_info(dev, "R[%d]_OUT_CONTROL[0x%llx]: 0x%016llx\n",
78 qno, CN93_SDP_R_OUT_CONTROL(qno),
79 octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(qno)));
80 dev_info(dev, "R[%d]_OUT_ENABLE[0x%llx]: 0x%016llx\n",
81 qno, CN93_SDP_R_OUT_ENABLE(qno),
82 octep_read_csr64(oct, CN93_SDP_R_OUT_ENABLE(qno)));
83 dev_info(dev, "R[%d]_OUT_SLIST_BADDR[0x%llx]: 0x%016llx\n",
84 qno, CN93_SDP_R_OUT_SLIST_BADDR(qno),
85 octep_read_csr64(oct, CN93_SDP_R_OUT_SLIST_BADDR(qno)));
86 dev_info(dev, "R[%d]_OUT_SLIST_RSIZE[0x%llx]: 0x%016llx\n",
87 qno, CN93_SDP_R_OUT_SLIST_RSIZE(qno),
88 octep_read_csr64(oct, CN93_SDP_R_OUT_SLIST_RSIZE(qno)));
89 dev_info(dev, "R[%d]_OUT_CNTS[0x%llx]: 0x%016llx\n",
90 qno, CN93_SDP_R_OUT_CNTS(qno),
91 octep_read_csr64(oct, CN93_SDP_R_OUT_CNTS(qno)));
92 dev_info(dev, "R[%d]_OUT_INT_LEVELS[0x%llx]: 0x%016llx\n",
93 qno, CN93_SDP_R_OUT_INT_LEVELS(qno),
94 octep_read_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(qno)));
95 dev_info(dev, "R[%d]_OUT_PKT_CNT[0x%llx]: 0x%016llx\n",
96 qno, CN93_SDP_R_OUT_PKT_CNT(qno),
97 octep_read_csr64(oct, CN93_SDP_R_OUT_PKT_CNT(qno)));
98 dev_info(dev, "R[%d]_OUT_BYTE_CNT[0x%llx]: 0x%016llx\n",
99 qno, CN93_SDP_R_OUT_BYTE_CNT(qno),
100 octep_read_csr64(oct, CN93_SDP_R_OUT_BYTE_CNT(qno)));
101 dev_info(dev, "R[%d]_ERR_TYPE[0x%llx]: 0x%016llx\n",
102 qno, CN93_SDP_R_ERR_TYPE(qno),
103 octep_read_csr64(oct, CN93_SDP_R_ERR_TYPE(qno)));
104 }
105
106 /* Reset Hardware Tx queue */
cn93_reset_iq(struct octep_device * oct,int q_no)107 static int cn93_reset_iq(struct octep_device *oct, int q_no)
108 {
109 struct octep_config *conf = oct->conf;
110 u64 val = 0ULL;
111
112 dev_dbg(&oct->pdev->dev, "Reset PF IQ-%d\n", q_no);
113
114 /* Get absolute queue number */
115 q_no += conf->pf_ring_cfg.srn;
116
117 /* Disable the Tx/Instruction Ring */
118 octep_write_csr64(oct, CN93_SDP_R_IN_ENABLE(q_no), val);
119
120 /* clear the Instruction Ring packet/byte counts and doorbell CSRs */
121 octep_write_csr64(oct, CN93_SDP_R_IN_CNTS(q_no), val);
122 octep_write_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(q_no), val);
123 octep_write_csr64(oct, CN93_SDP_R_IN_PKT_CNT(q_no), val);
124 octep_write_csr64(oct, CN93_SDP_R_IN_BYTE_CNT(q_no), val);
125 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_BADDR(q_no), val);
126 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_RSIZE(q_no), val);
127
128 val = 0xFFFFFFFF;
129 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_DBELL(q_no), val);
130
131 return 0;
132 }
133
134 /* Reset Hardware Rx queue */
cn93_reset_oq(struct octep_device * oct,int q_no)135 static void cn93_reset_oq(struct octep_device *oct, int q_no)
136 {
137 u64 val = 0ULL;
138
139 q_no += CFG_GET_PORTS_PF_SRN(oct->conf);
140
141 /* Disable Output (Rx) Ring */
142 octep_write_csr64(oct, CN93_SDP_R_OUT_ENABLE(q_no), val);
143
144 /* Clear count CSRs */
145 val = octep_read_csr(oct, CN93_SDP_R_OUT_CNTS(q_no));
146 octep_write_csr(oct, CN93_SDP_R_OUT_CNTS(q_no), val);
147
148 octep_write_csr64(oct, CN93_SDP_R_OUT_PKT_CNT(q_no), 0xFFFFFFFFFULL);
149 octep_write_csr64(oct, CN93_SDP_R_OUT_SLIST_DBELL(q_no), 0xFFFFFFFF);
150 }
151
152 /* Reset all hardware Tx/Rx queues */
octep_reset_io_queues_cn93_pf(struct octep_device * oct)153 static void octep_reset_io_queues_cn93_pf(struct octep_device *oct)
154 {
155 struct pci_dev *pdev = oct->pdev;
156 int q;
157
158 dev_dbg(&pdev->dev, "Reset OCTEP_CN93 PF IO Queues\n");
159
160 for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); q++) {
161 cn93_reset_iq(oct, q);
162 cn93_reset_oq(oct, q);
163 }
164 }
165
166 /* Initialize windowed addresses to access some hardware registers */
octep_setup_pci_window_regs_cn93_pf(struct octep_device * oct)167 static void octep_setup_pci_window_regs_cn93_pf(struct octep_device *oct)
168 {
169 u8 __iomem *bar0_pciaddr = oct->mmio[0].hw_addr;
170
171 oct->pci_win_regs.pci_win_wr_addr = (u8 __iomem *)(bar0_pciaddr + CN93_SDP_WIN_WR_ADDR64);
172 oct->pci_win_regs.pci_win_rd_addr = (u8 __iomem *)(bar0_pciaddr + CN93_SDP_WIN_RD_ADDR64);
173 oct->pci_win_regs.pci_win_wr_data = (u8 __iomem *)(bar0_pciaddr + CN93_SDP_WIN_WR_DATA64);
174 oct->pci_win_regs.pci_win_rd_data = (u8 __iomem *)(bar0_pciaddr + CN93_SDP_WIN_RD_DATA64);
175 }
176
177 /* Configure Hardware mapping: inform hardware which rings belong to PF. */
octep_configure_ring_mapping_cn93_pf(struct octep_device * oct)178 static void octep_configure_ring_mapping_cn93_pf(struct octep_device *oct)
179 {
180 struct octep_config *conf = oct->conf;
181 struct pci_dev *pdev = oct->pdev;
182 u64 pf_srn = CFG_GET_PORTS_PF_SRN(oct->conf);
183 int q;
184
185 for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(conf); q++) {
186 u64 regval = 0;
187
188 if (oct->pcie_port)
189 regval = 8 << CN93_SDP_FUNC_SEL_EPF_BIT_POS;
190
191 octep_write_csr64(oct, CN93_SDP_EPVF_RING(pf_srn + q), regval);
192
193 regval = octep_read_csr64(oct, CN93_SDP_EPVF_RING(pf_srn + q));
194 dev_dbg(&pdev->dev, "Write SDP_EPVF_RING[0x%llx] = 0x%llx\n",
195 CN93_SDP_EPVF_RING(pf_srn + q), regval);
196 }
197 }
198
199 /* Initialize configuration limits and initial active config 93xx PF. */
octep_init_config_cn93_pf(struct octep_device * oct)200 static void octep_init_config_cn93_pf(struct octep_device *oct)
201 {
202 struct octep_config *conf = oct->conf;
203 struct pci_dev *pdev = oct->pdev;
204 u8 link = 0;
205 u64 val;
206 int pos;
207
208 /* Read ring configuration:
209 * PF ring count, number of VFs and rings per VF supported
210 */
211 val = octep_read_csr64(oct, CN93_SDP_EPF_RINFO);
212 conf->sriov_cfg.max_rings_per_vf = CN93_SDP_EPF_RINFO_RPVF(val);
213 conf->sriov_cfg.active_rings_per_vf = conf->sriov_cfg.max_rings_per_vf;
214 conf->sriov_cfg.max_vfs = CN93_SDP_EPF_RINFO_NVFS(val);
215 conf->sriov_cfg.active_vfs = conf->sriov_cfg.max_vfs;
216 conf->sriov_cfg.vf_srn = CN93_SDP_EPF_RINFO_SRN(val);
217
218 val = octep_read_csr64(oct, CN93_SDP_MAC_PF_RING_CTL(oct->pcie_port));
219 if (oct->chip_id == OCTEP_PCI_DEVICE_ID_CN98_PF) {
220 conf->pf_ring_cfg.srn = CN98_SDP_MAC_PF_RING_CTL_SRN(val);
221 conf->pf_ring_cfg.max_io_rings = CN98_SDP_MAC_PF_RING_CTL_RPPF(val);
222 conf->pf_ring_cfg.active_io_rings = conf->pf_ring_cfg.max_io_rings;
223 } else {
224 conf->pf_ring_cfg.srn = CN93_SDP_MAC_PF_RING_CTL_SRN(val);
225 conf->pf_ring_cfg.max_io_rings = CN93_SDP_MAC_PF_RING_CTL_RPPF(val);
226 conf->pf_ring_cfg.active_io_rings = conf->pf_ring_cfg.max_io_rings;
227 }
228 dev_info(&pdev->dev, "pf_srn=%u rpvf=%u nvfs=%u rppf=%u\n",
229 conf->pf_ring_cfg.srn, conf->sriov_cfg.active_rings_per_vf,
230 conf->sriov_cfg.active_vfs, conf->pf_ring_cfg.active_io_rings);
231
232 conf->iq.num_descs = OCTEP_IQ_MAX_DESCRIPTORS;
233 conf->iq.instr_type = OCTEP_64BYTE_INSTR;
234 conf->iq.db_min = OCTEP_DB_MIN;
235 conf->iq.intr_threshold = OCTEP_IQ_INTR_THRESHOLD;
236
237 conf->oq.num_descs = OCTEP_OQ_MAX_DESCRIPTORS;
238 conf->oq.buf_size = OCTEP_OQ_BUF_SIZE;
239 conf->oq.refill_threshold = OCTEP_OQ_REFILL_THRESHOLD;
240 conf->oq.oq_intr_pkt = OCTEP_OQ_INTR_PKT_THRESHOLD;
241 conf->oq.oq_intr_time = OCTEP_OQ_INTR_TIME_THRESHOLD;
242
243 conf->msix_cfg.non_ioq_msix = CN93_NUM_NON_IOQ_INTR;
244 conf->msix_cfg.ioq_msix = conf->pf_ring_cfg.active_io_rings;
245 conf->msix_cfg.non_ioq_msix_names = cn93_non_ioq_msix_names;
246
247 pos = pci_find_ext_capability(oct->pdev, PCI_EXT_CAP_ID_SRIOV);
248 if (pos) {
249 pci_read_config_byte(oct->pdev,
250 pos + PCI_SRIOV_FUNC_LINK,
251 &link);
252 link = PCI_DEVFN(PCI_SLOT(oct->pdev->devfn), link);
253 }
254 conf->ctrl_mbox_cfg.barmem_addr = (void __iomem *)oct->mmio[2].hw_addr +
255 CN93_PEM_BAR4_INDEX_OFFSET +
256 (link * CTRL_MBOX_SZ);
257
258 conf->fw_info.hb_interval = OCTEP_DEFAULT_FW_HB_INTERVAL;
259 conf->fw_info.hb_miss_count = OCTEP_DEFAULT_FW_HB_MISS_COUNT;
260 }
261
262 /* Setup registers for a hardware Tx Queue */
octep_setup_iq_regs_cn93_pf(struct octep_device * oct,int iq_no)263 static void octep_setup_iq_regs_cn93_pf(struct octep_device *oct, int iq_no)
264 {
265 struct octep_iq *iq = oct->iq[iq_no];
266 u32 reset_instr_cnt;
267 u64 reg_val;
268
269 iq_no += CFG_GET_PORTS_PF_SRN(oct->conf);
270 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no));
271
272 /* wait for IDLE to set to 1 */
273 if (!(reg_val & CN93_R_IN_CTL_IDLE)) {
274 do {
275 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no));
276 } while (!(reg_val & CN93_R_IN_CTL_IDLE));
277 }
278
279 reg_val |= CN93_R_IN_CTL_RDSIZE;
280 reg_val |= CN93_R_IN_CTL_IS_64B;
281 reg_val |= CN93_R_IN_CTL_ESR;
282 octep_write_csr64(oct, CN93_SDP_R_IN_CONTROL(iq_no), reg_val);
283
284 /* Write the start of the input queue's ring and its size */
285 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_BADDR(iq_no),
286 iq->desc_ring_dma);
287 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_RSIZE(iq_no),
288 iq->max_count);
289
290 /* Remember the doorbell & instruction count register addr
291 * for this queue
292 */
293 iq->doorbell_reg = oct->mmio[0].hw_addr +
294 CN93_SDP_R_IN_INSTR_DBELL(iq_no);
295 iq->inst_cnt_reg = oct->mmio[0].hw_addr +
296 CN93_SDP_R_IN_CNTS(iq_no);
297 iq->intr_lvl_reg = oct->mmio[0].hw_addr +
298 CN93_SDP_R_IN_INT_LEVELS(iq_no);
299
300 /* Store the current instruction counter (used in flush_iq calculation) */
301 reset_instr_cnt = readl(iq->inst_cnt_reg);
302 writel(reset_instr_cnt, iq->inst_cnt_reg);
303
304 /* INTR_THRESHOLD is set to max(FFFFFFFF) to disable the INTR */
305 reg_val = CFG_GET_IQ_INTR_THRESHOLD(oct->conf) & 0xffffffff;
306 octep_write_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(iq_no), reg_val);
307 }
308
309 /* Setup registers for a hardware Rx Queue */
octep_setup_oq_regs_cn93_pf(struct octep_device * oct,int oq_no)310 static void octep_setup_oq_regs_cn93_pf(struct octep_device *oct, int oq_no)
311 {
312 u64 reg_val;
313 u64 oq_ctl = 0ULL;
314 u32 time_threshold = 0;
315 struct octep_oq *oq = oct->oq[oq_no];
316
317 oq_no += CFG_GET_PORTS_PF_SRN(oct->conf);
318 reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no));
319
320 /* wait for IDLE to set to 1 */
321 if (!(reg_val & CN93_R_OUT_CTL_IDLE)) {
322 do {
323 reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no));
324 } while (!(reg_val & CN93_R_OUT_CTL_IDLE));
325 }
326
327 reg_val &= ~(CN93_R_OUT_CTL_IMODE);
328 reg_val &= ~(CN93_R_OUT_CTL_ROR_P);
329 reg_val &= ~(CN93_R_OUT_CTL_NSR_P);
330 reg_val &= ~(CN93_R_OUT_CTL_ROR_I);
331 reg_val &= ~(CN93_R_OUT_CTL_NSR_I);
332 reg_val &= ~(CN93_R_OUT_CTL_ES_I);
333 reg_val &= ~(CN93_R_OUT_CTL_ROR_D);
334 reg_val &= ~(CN93_R_OUT_CTL_NSR_D);
335 reg_val &= ~(CN93_R_OUT_CTL_ES_D);
336 reg_val |= (CN93_R_OUT_CTL_ES_P);
337
338 octep_write_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no), reg_val);
339 octep_write_csr64(oct, CN93_SDP_R_OUT_SLIST_BADDR(oq_no),
340 oq->desc_ring_dma);
341 octep_write_csr64(oct, CN93_SDP_R_OUT_SLIST_RSIZE(oq_no),
342 oq->max_count);
343
344 oq_ctl = octep_read_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no));
345 oq_ctl &= ~0x7fffffULL; //clear the ISIZE and BSIZE (22-0)
346 oq_ctl |= (oq->buffer_size & 0xffff); //populate the BSIZE (15-0)
347 octep_write_csr64(oct, CN93_SDP_R_OUT_CONTROL(oq_no), oq_ctl);
348
349 /* Get the mapped address of the pkt_sent and pkts_credit regs */
350 oq->pkts_sent_reg = oct->mmio[0].hw_addr + CN93_SDP_R_OUT_CNTS(oq_no);
351 oq->pkts_credit_reg = oct->mmio[0].hw_addr +
352 CN93_SDP_R_OUT_SLIST_DBELL(oq_no);
353
354 time_threshold = CFG_GET_OQ_INTR_TIME(oct->conf);
355 reg_val = ((u64)time_threshold << 32) |
356 CFG_GET_OQ_INTR_PKT(oct->conf);
357 octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);
358 }
359
360 /* Setup registers for a PF mailbox */
octep_setup_mbox_regs_cn93_pf(struct octep_device * oct,int q_no)361 static void octep_setup_mbox_regs_cn93_pf(struct octep_device *oct, int q_no)
362 {
363 struct octep_mbox *mbox = oct->mbox[q_no];
364
365 /* PF to VF DATA reg. PF writes into this reg */
366 mbox->pf_vf_data_reg = oct->mmio[0].hw_addr + CN93_SDP_MBOX_PF_VF_DATA(q_no);
367
368 /* VF to PF DATA reg. PF reads from this reg */
369 mbox->vf_pf_data_reg = oct->mmio[0].hw_addr + CN93_SDP_MBOX_VF_PF_DATA(q_no);
370 }
371
372 /* Poll for mailbox messages from VF */
octep_poll_pfvf_mailbox(struct octep_device * oct)373 static void octep_poll_pfvf_mailbox(struct octep_device *oct)
374 {
375 u32 vf, active_vfs, active_rings_per_vf, vf_mbox_queue;
376 u64 reg0, reg1;
377
378 reg0 = octep_read_csr64(oct, CN93_SDP_EPF_MBOX_RINT(0));
379 reg1 = octep_read_csr64(oct, CN93_SDP_EPF_MBOX_RINT(1));
380 if (reg0 || reg1) {
381 active_vfs = CFG_GET_ACTIVE_VFS(oct->conf);
382 active_rings_per_vf = CFG_GET_ACTIVE_RPVF(oct->conf);
383 for (vf = 0; vf < active_vfs; vf++) {
384 vf_mbox_queue = vf * active_rings_per_vf;
385
386 if (vf_mbox_queue < 64) {
387 if (!(reg0 & (0x1UL << vf_mbox_queue)))
388 continue;
389 } else {
390 if (!(reg1 & (0x1UL << (vf_mbox_queue - 64))))
391 continue;
392 }
393
394 if (!oct->mbox[vf_mbox_queue]) {
395 dev_err(&oct->pdev->dev, "bad mbox vf %d\n", vf);
396 continue;
397 }
398 schedule_work(&oct->mbox[vf_mbox_queue]->wk.work);
399 }
400 if (reg0)
401 octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT(0), reg0);
402 if (reg1)
403 octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT(1), reg1);
404 }
405 }
406
407 /* PF-VF mailbox interrupt handler */
octep_pfvf_mbox_intr_handler_cn93_pf(void * dev)408 static irqreturn_t octep_pfvf_mbox_intr_handler_cn93_pf(void *dev)
409 {
410 struct octep_device *oct = (struct octep_device *)dev;
411
412 octep_poll_pfvf_mailbox(oct);
413 return IRQ_HANDLED;
414 }
415
416 /* Poll OEI events like heartbeat */
octep_poll_oei_cn93_pf(struct octep_device * oct)417 static void octep_poll_oei_cn93_pf(struct octep_device *oct)
418 {
419 u64 reg;
420
421 reg = octep_read_csr64(oct, CN93_SDP_EPF_OEI_RINT);
422 if (reg) {
423 octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT, reg);
424 if (reg & CN93_SDP_EPF_OEI_RINT_DATA_BIT_MBOX)
425 queue_work(octep_wq, &oct->ctrl_mbox_task);
426 else if (reg & CN93_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT)
427 atomic_set(&oct->hb_miss_cnt, 0);
428 }
429 }
430
431 /* OEI interrupt handler */
octep_oei_intr_handler_cn93_pf(void * dev)432 static irqreturn_t octep_oei_intr_handler_cn93_pf(void *dev)
433 {
434 struct octep_device *oct = (struct octep_device *)dev;
435
436 octep_poll_oei_cn93_pf(oct);
437 return IRQ_HANDLED;
438 }
439
440 /* Process non-ioq interrupts required to keep pf interface running.
441 * OEI_RINT is needed for control mailbox
442 */
octep_poll_non_ioq_interrupts_cn93_pf(struct octep_device * oct)443 static void octep_poll_non_ioq_interrupts_cn93_pf(struct octep_device *oct)
444 {
445 octep_poll_pfvf_mailbox(oct);
446 octep_poll_oei_cn93_pf(oct);
447 }
448
449 /* Interrupt handler for input ring error interrupts. */
octep_ire_intr_handler_cn93_pf(void * dev)450 static irqreturn_t octep_ire_intr_handler_cn93_pf(void *dev)
451 {
452 struct octep_device *oct = (struct octep_device *)dev;
453 struct pci_dev *pdev = oct->pdev;
454 u64 reg_val = 0;
455 int i = 0;
456
457 /* Check for IRERR INTR */
458 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_IRERR_RINT);
459 if (reg_val) {
460 dev_info(&pdev->dev,
461 "received IRERR_RINT intr: 0x%llx\n", reg_val);
462 octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT, reg_val);
463
464 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++) {
465 reg_val = octep_read_csr64(oct,
466 CN93_SDP_R_ERR_TYPE(i));
467 if (reg_val) {
468 dev_info(&pdev->dev,
469 "Received err type on IQ-%d: 0x%llx\n",
470 i, reg_val);
471 octep_write_csr64(oct, CN93_SDP_R_ERR_TYPE(i),
472 reg_val);
473 }
474 }
475 }
476 return IRQ_HANDLED;
477 }
478
479 /* Interrupt handler for output ring error interrupts. */
octep_ore_intr_handler_cn93_pf(void * dev)480 static irqreturn_t octep_ore_intr_handler_cn93_pf(void *dev)
481 {
482 struct octep_device *oct = (struct octep_device *)dev;
483 struct pci_dev *pdev = oct->pdev;
484 u64 reg_val = 0;
485 int i = 0;
486
487 /* Check for ORERR INTR */
488 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_ORERR_RINT);
489 if (reg_val) {
490 dev_info(&pdev->dev,
491 "Received ORERR_RINT intr: 0x%llx\n", reg_val);
492 octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT, reg_val);
493 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++) {
494 reg_val = octep_read_csr64(oct, CN93_SDP_R_ERR_TYPE(i));
495 if (reg_val) {
496 dev_info(&pdev->dev,
497 "Received err type on OQ-%d: 0x%llx\n",
498 i, reg_val);
499 octep_write_csr64(oct, CN93_SDP_R_ERR_TYPE(i),
500 reg_val);
501 }
502 }
503 }
504 return IRQ_HANDLED;
505 }
506
507 /* Interrupt handler for vf input ring error interrupts. */
octep_vfire_intr_handler_cn93_pf(void * dev)508 static irqreturn_t octep_vfire_intr_handler_cn93_pf(void *dev)
509 {
510 struct octep_device *oct = (struct octep_device *)dev;
511 struct pci_dev *pdev = oct->pdev;
512 u64 reg_val = 0;
513
514 /* Check for VFIRE INTR */
515 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_VFIRE_RINT(0));
516 if (reg_val) {
517 dev_info(&pdev->dev,
518 "Received VFIRE_RINT intr: 0x%llx\n", reg_val);
519 octep_write_csr64(oct, CN93_SDP_EPF_VFIRE_RINT(0), reg_val);
520 }
521 return IRQ_HANDLED;
522 }
523
524 /* Interrupt handler for vf output ring error interrupts. */
octep_vfore_intr_handler_cn93_pf(void * dev)525 static irqreturn_t octep_vfore_intr_handler_cn93_pf(void *dev)
526 {
527 struct octep_device *oct = (struct octep_device *)dev;
528 struct pci_dev *pdev = oct->pdev;
529 u64 reg_val = 0;
530
531 /* Check for VFORE INTR */
532 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_VFORE_RINT(0));
533 if (reg_val) {
534 dev_info(&pdev->dev,
535 "Received VFORE_RINT intr: 0x%llx\n", reg_val);
536 octep_write_csr64(oct, CN93_SDP_EPF_VFORE_RINT(0), reg_val);
537 }
538 return IRQ_HANDLED;
539 }
540
541 /* Interrupt handler for dpi dma related interrupts. */
octep_dma_intr_handler_cn93_pf(void * dev)542 static irqreturn_t octep_dma_intr_handler_cn93_pf(void *dev)
543 {
544 struct octep_device *oct = (struct octep_device *)dev;
545 u64 reg_val = 0;
546
547 /* Check for DMA INTR */
548 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_DMA_RINT);
549 if (reg_val) {
550 octep_write_csr64(oct, CN93_SDP_EPF_DMA_RINT, reg_val);
551 }
552 return IRQ_HANDLED;
553 }
554
555 /* Interrupt handler for dpi dma transaction error interrupts for VFs */
octep_dma_vf_intr_handler_cn93_pf(void * dev)556 static irqreturn_t octep_dma_vf_intr_handler_cn93_pf(void *dev)
557 {
558 struct octep_device *oct = (struct octep_device *)dev;
559 struct pci_dev *pdev = oct->pdev;
560 u64 reg_val = 0;
561
562 /* Check for DMA VF INTR */
563 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT(0));
564 if (reg_val) {
565 dev_info(&pdev->dev,
566 "Received DMA_VF_RINT intr: 0x%llx\n", reg_val);
567 octep_write_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT(0), reg_val);
568 }
569 return IRQ_HANDLED;
570 }
571
572 /* Interrupt handler for pp transaction error interrupts for VFs */
octep_pp_vf_intr_handler_cn93_pf(void * dev)573 static irqreturn_t octep_pp_vf_intr_handler_cn93_pf(void *dev)
574 {
575 struct octep_device *oct = (struct octep_device *)dev;
576 struct pci_dev *pdev = oct->pdev;
577 u64 reg_val = 0;
578
579 /* Check for PPVF INTR */
580 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_PP_VF_RINT(0));
581 if (reg_val) {
582 dev_info(&pdev->dev,
583 "Received PP_VF_RINT intr: 0x%llx\n", reg_val);
584 octep_write_csr64(oct, CN93_SDP_EPF_PP_VF_RINT(0), reg_val);
585 }
586 return IRQ_HANDLED;
587 }
588
589 /* Interrupt handler for mac related interrupts. */
octep_misc_intr_handler_cn93_pf(void * dev)590 static irqreturn_t octep_misc_intr_handler_cn93_pf(void *dev)
591 {
592 struct octep_device *oct = (struct octep_device *)dev;
593 struct pci_dev *pdev = oct->pdev;
594 u64 reg_val = 0;
595
596 /* Check for MISC INTR */
597 reg_val = octep_read_csr64(oct, CN93_SDP_EPF_MISC_RINT);
598 if (reg_val) {
599 dev_info(&pdev->dev,
600 "Received MISC_RINT intr: 0x%llx\n", reg_val);
601 octep_write_csr64(oct, CN93_SDP_EPF_MISC_RINT, reg_val);
602 }
603 return IRQ_HANDLED;
604 }
605
606 /* Interrupts handler for all reserved interrupts. */
octep_rsvd_intr_handler_cn93_pf(void * dev)607 static irqreturn_t octep_rsvd_intr_handler_cn93_pf(void *dev)
608 {
609 struct octep_device *oct = (struct octep_device *)dev;
610 struct pci_dev *pdev = oct->pdev;
611
612 dev_info(&pdev->dev, "Reserved interrupts raised; Ignore\n");
613 return IRQ_HANDLED;
614 }
615
616 /* Tx/Rx queue interrupt handler */
octep_ioq_intr_handler_cn93_pf(void * data)617 static irqreturn_t octep_ioq_intr_handler_cn93_pf(void *data)
618 {
619 struct octep_ioq_vector *vector = (struct octep_ioq_vector *)data;
620 struct octep_oq *oq = vector->oq;
621
622 napi_schedule_irqoff(oq->napi);
623 return IRQ_HANDLED;
624 }
625
626 /* soft reset of 98xx */
octep_soft_reset_cn98_pf(struct octep_device * oct)627 static int octep_soft_reset_cn98_pf(struct octep_device *oct)
628 {
629 dev_info(&oct->pdev->dev, "CN98XX: skip soft reset\n");
630 return 0;
631 }
632
633 /* soft reset of 93xx */
octep_soft_reset_cn93_pf(struct octep_device * oct)634 static int octep_soft_reset_cn93_pf(struct octep_device *oct)
635 {
636 dev_info(&oct->pdev->dev, "CN93XX: Doing soft reset\n");
637
638 octep_write_csr64(oct, CN93_SDP_WIN_WR_MASK_REG, 0xFF);
639
640 /* Set core domain reset bit */
641 OCTEP_PCI_WIN_WRITE(oct, CN93_RST_CORE_DOMAIN_W1S, 1);
642 /* Wait for 100ms as Octeon resets. */
643 mdelay(100);
644 /* clear core domain reset bit */
645 OCTEP_PCI_WIN_WRITE(oct, CN93_RST_CORE_DOMAIN_W1C, 1);
646
647 return 0;
648 }
649
650 /* Re-initialize Octeon hardware registers */
octep_reinit_regs_cn93_pf(struct octep_device * oct)651 static void octep_reinit_regs_cn93_pf(struct octep_device *oct)
652 {
653 u32 i;
654
655 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++)
656 oct->hw_ops.setup_iq_regs(oct, i);
657
658 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++)
659 oct->hw_ops.setup_oq_regs(oct, i);
660
661 oct->hw_ops.enable_interrupts(oct);
662 oct->hw_ops.enable_io_queues(oct);
663
664 for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++)
665 writel(oct->oq[i]->max_count, oct->oq[i]->pkts_credit_reg);
666 }
667
668 /* Enable all interrupts */
octep_enable_interrupts_cn93_pf(struct octep_device * oct)669 static void octep_enable_interrupts_cn93_pf(struct octep_device *oct)
670 {
671 u64 intr_mask = 0ULL;
672 int srn, num_rings, i;
673
674 srn = CFG_GET_PORTS_PF_SRN(oct->conf);
675 num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf);
676
677 for (i = 0; i < num_rings; i++)
678 intr_mask |= (0x1ULL << (srn + i));
679
680 octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT_ENA_W1S, intr_mask);
681 octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT_ENA_W1S, intr_mask);
682 octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT_ENA_W1S, -1ULL);
683
684 octep_write_csr64(oct, CN93_SDP_EPF_VFIRE_RINT_ENA_W1S(0), -1ULL);
685 octep_write_csr64(oct, CN93_SDP_EPF_VFORE_RINT_ENA_W1S(0), -1ULL);
686
687 octep_write_csr64(oct, CN93_SDP_EPF_MISC_RINT_ENA_W1S, intr_mask);
688 octep_write_csr64(oct, CN93_SDP_EPF_DMA_RINT_ENA_W1S, intr_mask);
689 octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT_ENA_W1S(0), -1ULL);
690 octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT_ENA_W1S(1), -1ULL);
691
692 octep_write_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT_ENA_W1S(0), -1ULL);
693 octep_write_csr64(oct, CN93_SDP_EPF_PP_VF_RINT_ENA_W1S(0), -1ULL);
694 }
695
696 /* Disable all interrupts */
octep_disable_interrupts_cn93_pf(struct octep_device * oct)697 static void octep_disable_interrupts_cn93_pf(struct octep_device *oct)
698 {
699 u64 intr_mask = 0ULL;
700 int srn, num_rings, i;
701
702 srn = CFG_GET_PORTS_PF_SRN(oct->conf);
703 num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf);
704
705 for (i = 0; i < num_rings; i++)
706 intr_mask |= (0x1ULL << (srn + i));
707
708 octep_write_csr64(oct, CN93_SDP_EPF_IRERR_RINT_ENA_W1C, intr_mask);
709 octep_write_csr64(oct, CN93_SDP_EPF_ORERR_RINT_ENA_W1C, intr_mask);
710 octep_write_csr64(oct, CN93_SDP_EPF_OEI_RINT_ENA_W1C, -1ULL);
711
712 octep_write_csr64(oct, CN93_SDP_EPF_VFIRE_RINT_ENA_W1C(0), -1ULL);
713 octep_write_csr64(oct, CN93_SDP_EPF_VFORE_RINT_ENA_W1C(0), -1ULL);
714
715 octep_write_csr64(oct, CN93_SDP_EPF_MISC_RINT_ENA_W1C, intr_mask);
716 octep_write_csr64(oct, CN93_SDP_EPF_DMA_RINT_ENA_W1C, intr_mask);
717 octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT_ENA_W1C(0), -1ULL);
718 octep_write_csr64(oct, CN93_SDP_EPF_MBOX_RINT_ENA_W1C(1), -1ULL);
719
720 octep_write_csr64(oct, CN93_SDP_EPF_DMA_VF_RINT_ENA_W1C(0), -1ULL);
721 octep_write_csr64(oct, CN93_SDP_EPF_PP_VF_RINT_ENA_W1C(0), -1ULL);
722 }
723
724 /* Get new Octeon Read Index: index of descriptor that Octeon reads next. */
octep_update_iq_read_index_cn93_pf(struct octep_iq * iq)725 static u32 octep_update_iq_read_index_cn93_pf(struct octep_iq *iq)
726 {
727 u32 pkt_in_done = readl(iq->inst_cnt_reg);
728 u32 last_done, new_idx;
729
730 last_done = pkt_in_done - iq->pkt_in_done;
731 iq->pkt_in_done = pkt_in_done;
732
733 new_idx = (iq->octep_read_index + last_done) % iq->max_count;
734
735 return new_idx;
736 }
737
738 /* Enable a hardware Tx Queue */
octep_enable_iq_cn93_pf(struct octep_device * oct,int iq_no)739 static void octep_enable_iq_cn93_pf(struct octep_device *oct, int iq_no)
740 {
741 u64 loop = HZ;
742 u64 reg_val;
743
744 iq_no += CFG_GET_PORTS_PF_SRN(oct->conf);
745
746 octep_write_csr64(oct, CN93_SDP_R_IN_INSTR_DBELL(iq_no), 0xFFFFFFFF);
747
748 while (octep_read_csr64(oct, CN93_SDP_R_IN_INSTR_DBELL(iq_no)) &&
749 loop--) {
750 schedule_timeout_interruptible(1);
751 }
752
753 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(iq_no));
754 reg_val |= (0x1ULL << 62);
755 octep_write_csr64(oct, CN93_SDP_R_IN_INT_LEVELS(iq_no), reg_val);
756
757 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no));
758 reg_val |= 0x1ULL;
759 octep_write_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no), reg_val);
760 }
761
762 /* Enable a hardware Rx Queue */
octep_enable_oq_cn93_pf(struct octep_device * oct,int oq_no)763 static void octep_enable_oq_cn93_pf(struct octep_device *oct, int oq_no)
764 {
765 u64 reg_val = 0ULL;
766
767 oq_no += CFG_GET_PORTS_PF_SRN(oct->conf);
768
769 reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no));
770 reg_val |= (0x1ULL << 62);
771 octep_write_csr64(oct, CN93_SDP_R_OUT_INT_LEVELS(oq_no), reg_val);
772
773 octep_write_csr64(oct, CN93_SDP_R_OUT_SLIST_DBELL(oq_no), 0xFFFFFFFF);
774
775 reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no));
776 reg_val |= 0x1ULL;
777 octep_write_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no), reg_val);
778 }
779
780 /* Enable all hardware Tx/Rx Queues assined to PF */
octep_enable_io_queues_cn93_pf(struct octep_device * oct)781 static void octep_enable_io_queues_cn93_pf(struct octep_device *oct)
782 {
783 u8 q;
784
785 for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); q++) {
786 octep_enable_iq_cn93_pf(oct, q);
787 octep_enable_oq_cn93_pf(oct, q);
788 }
789 }
790
791 /* Disable a hardware Tx Queue assined to PF */
octep_disable_iq_cn93_pf(struct octep_device * oct,int iq_no)792 static void octep_disable_iq_cn93_pf(struct octep_device *oct, int iq_no)
793 {
794 u64 reg_val = 0ULL;
795
796 iq_no += CFG_GET_PORTS_PF_SRN(oct->conf);
797
798 reg_val = octep_read_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no));
799 reg_val &= ~0x1ULL;
800 octep_write_csr64(oct, CN93_SDP_R_IN_ENABLE(iq_no), reg_val);
801 }
802
803 /* Disable a hardware Rx Queue assined to PF */
octep_disable_oq_cn93_pf(struct octep_device * oct,int oq_no)804 static void octep_disable_oq_cn93_pf(struct octep_device *oct, int oq_no)
805 {
806 u64 reg_val = 0ULL;
807
808 oq_no += CFG_GET_PORTS_PF_SRN(oct->conf);
809 reg_val = octep_read_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no));
810 reg_val &= ~0x1ULL;
811 octep_write_csr64(oct, CN93_SDP_R_OUT_ENABLE(oq_no), reg_val);
812 }
813
814 /* Disable all hardware Tx/Rx Queues assined to PF */
octep_disable_io_queues_cn93_pf(struct octep_device * oct)815 static void octep_disable_io_queues_cn93_pf(struct octep_device *oct)
816 {
817 int q = 0;
818
819 for (q = 0; q < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); q++) {
820 octep_disable_iq_cn93_pf(oct, q);
821 octep_disable_oq_cn93_pf(oct, q);
822 }
823 }
824
825 /* Dump hardware registers (including Tx/Rx queues) for debugging. */
octep_dump_registers_cn93_pf(struct octep_device * oct)826 static void octep_dump_registers_cn93_pf(struct octep_device *oct)
827 {
828 u8 srn, num_rings, q;
829
830 srn = CFG_GET_PORTS_PF_SRN(oct->conf);
831 num_rings = CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf);
832
833 for (q = srn; q < srn + num_rings; q++)
834 cn93_dump_regs(oct, q);
835 }
836
837 /**
838 * octep_device_setup_cn93_pf() - Setup Octeon device.
839 *
840 * @oct: Octeon device private data structure.
841 *
842 * - initialize hardware operations.
843 * - get target side pcie port number for the device.
844 * - setup window access to hardware registers.
845 * - set initial configuration and max limits.
846 * - setup hardware mapping of rings to the PF device.
847 */
octep_device_setup_cn93_pf(struct octep_device * oct)848 void octep_device_setup_cn93_pf(struct octep_device *oct)
849 {
850 oct->hw_ops.setup_iq_regs = octep_setup_iq_regs_cn93_pf;
851 oct->hw_ops.setup_oq_regs = octep_setup_oq_regs_cn93_pf;
852 oct->hw_ops.setup_mbox_regs = octep_setup_mbox_regs_cn93_pf;
853
854 oct->hw_ops.mbox_intr_handler = octep_pfvf_mbox_intr_handler_cn93_pf;
855 oct->hw_ops.oei_intr_handler = octep_oei_intr_handler_cn93_pf;
856 oct->hw_ops.ire_intr_handler = octep_ire_intr_handler_cn93_pf;
857 oct->hw_ops.ore_intr_handler = octep_ore_intr_handler_cn93_pf;
858 oct->hw_ops.vfire_intr_handler = octep_vfire_intr_handler_cn93_pf;
859 oct->hw_ops.vfore_intr_handler = octep_vfore_intr_handler_cn93_pf;
860 oct->hw_ops.dma_intr_handler = octep_dma_intr_handler_cn93_pf;
861 oct->hw_ops.dma_vf_intr_handler = octep_dma_vf_intr_handler_cn93_pf;
862 oct->hw_ops.pp_vf_intr_handler = octep_pp_vf_intr_handler_cn93_pf;
863 oct->hw_ops.misc_intr_handler = octep_misc_intr_handler_cn93_pf;
864 oct->hw_ops.rsvd_intr_handler = octep_rsvd_intr_handler_cn93_pf;
865 oct->hw_ops.ioq_intr_handler = octep_ioq_intr_handler_cn93_pf;
866 if (oct->chip_id == OCTEP_PCI_DEVICE_ID_CN98_PF)
867 oct->hw_ops.soft_reset = octep_soft_reset_cn98_pf;
868 else
869 oct->hw_ops.soft_reset = octep_soft_reset_cn93_pf;
870 oct->hw_ops.reinit_regs = octep_reinit_regs_cn93_pf;
871
872 oct->hw_ops.enable_interrupts = octep_enable_interrupts_cn93_pf;
873 oct->hw_ops.disable_interrupts = octep_disable_interrupts_cn93_pf;
874 oct->hw_ops.poll_non_ioq_interrupts = octep_poll_non_ioq_interrupts_cn93_pf;
875
876 oct->hw_ops.update_iq_read_idx = octep_update_iq_read_index_cn93_pf;
877
878 oct->hw_ops.enable_iq = octep_enable_iq_cn93_pf;
879 oct->hw_ops.enable_oq = octep_enable_oq_cn93_pf;
880 oct->hw_ops.enable_io_queues = octep_enable_io_queues_cn93_pf;
881
882 oct->hw_ops.disable_iq = octep_disable_iq_cn93_pf;
883 oct->hw_ops.disable_oq = octep_disable_oq_cn93_pf;
884 oct->hw_ops.disable_io_queues = octep_disable_io_queues_cn93_pf;
885 oct->hw_ops.reset_io_queues = octep_reset_io_queues_cn93_pf;
886
887 oct->hw_ops.dump_registers = octep_dump_registers_cn93_pf;
888
889 octep_setup_pci_window_regs_cn93_pf(oct);
890
891 oct->pcie_port = octep_read_csr64(oct, CN93_SDP_MAC_NUMBER) & 0xff;
892 dev_info(&oct->pdev->dev,
893 "Octeon device using PCIE Port %d\n", oct->pcie_port);
894
895 octep_init_config_cn93_pf(oct);
896 octep_configure_ring_mapping_cn93_pf(oct);
897 }
898