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/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
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/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
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/linux/arch/arm/mach-tegra/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-tegra/platsmp.c
12 #include <linux/clk/tegra.h>
21 #include <soc/tegra/flowctrl.h>
22 #include <soc/tegra/fuse.h>
23 #include <soc/tegra/pmc.h>
26 #include <asm/mach-types.h>
50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary()
58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary()
84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary()
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H A Dtegra.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * NVIDIA Tegra SoC device tree board support
11 #include <linux/clk/tegra.h>
12 #include <linux/dma-mapping.h>
30 #include <soc/tegra/fuse.h>
31 #include <soc/tegra/pmc.h>
34 #include <asm/hardware/cache-l2x0.h>
37 #include <asm/mach-types.h>
49 * Storage for debug-macro.S's state.
52 * kernel is loaded. The data is declared here rather than debug-macro.S so
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H A Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU complex suspend & resume functions for Tegra SoCs
5 * Copyright (c) 2009-2012, NVIDIA Corporation. All rights reserved.
8 #include <linux/clk/tegra.h>
21 #include <soc/tegra/flowctrl.h>
22 #include <soc/tegra/fuse.h>
23 #include <soc/tegra/pm.h>
24 #include <soc/tegra/pmc.h>
29 #include <asm/proc-fns.h>
141 if (tegra_cpu_car_ops->rail_off_ready && in tegra_sleep_cpu()
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/linux/drivers/soc/tegra/
H A Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
19 #include <linux/clk/tegra.h>
37 #include <linux/pinctrl/pinconf-generic.h>
52 #include <soc/tegra/common.h>
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H A Dregulators-tegra30.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2019 GRATE-DRIVER project
7 * Copyright (C) 2010-2011 NVIDIA Corporation
10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
21 #include <soc/tegra/fuse.h>
22 #include <soc/tegra/pmc.h>
43 static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, in tegra30_core_limit() argument
52 * Tegra30 SoC has critical DVFS-capable devices that are in tegra30_core_limit()
53 * permanently-active or active at a boot time, like EMC in tegra30_core_limit()
59 * the state of all DVFS-critical CORE devices is synced. in tegra30_core_limit()
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H A Dregulators-tegra20.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2019 GRATE-DRIVER project
7 * Copyright (C) 2010-2011 NVIDIA Corporation
10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt
21 #include <soc/tegra/fuse.h>
22 #include <soc/tegra/pmc.h>
44 static int tegra20_core_limit(struct tegra_regulator_coupler *tegra, in tegra20_core_limit() argument
53 * Tegra20 SoC has critical DVFS-capable devices that are in tegra20_core_limit()
54 * permanently-active or active at a boot time, like EMC in tegra20_core_limit()
60 * the state of all DVFS-critical CORE devices is synced. in tegra20_core_limit()
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/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra-audio-max9808x.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-max9808x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra audio complex with MAX9808x CODEC
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - items:
20 - pattern: '^[a-z0-9]+,tegra-audio-max98088(-[a-z0-9]+)+$'
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H A Dnvidia,tegra-audio-rt5631.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-rt5631.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra audio complex with RT5631 CODEC
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 - $ref: nvidia,tegra-audio-common.yaml#
19 - pattern: '^[a-z0-9]+,tegra-audio-rt5631(-[a-z0-9]+)+$'
20 - const: nvidia,tegra-audio-rt5631
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/linux/drivers/cpuidle/
H A Dcpuidle-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CPU idle driver for Tegra CPUs
5 * Copyright (c) 2010-2013, NVIDIA Corporation.
15 #define pr_fmt(fmt) "tegra-cpuidle: " fmt
26 #include <linux/clk/tegra.h>
29 #include <soc/tegra/cpuidle.h>
30 #include <soc/tegra/flowctrl.h>
31 #include <soc/tegra/fuse.h>
32 #include <soc/tegra/irq.h>
33 #include <soc/tegra/pm.h>
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/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
59 * Tegra CLK_OUT_ENB registers have some undefined bits which are not used and
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
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H A Dclk-tegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
14 #include <linux/clk/tegra.h>
16 #include <soc/tegra/pmc.h>
18 #include <dt-bindings/clock/tegra30-car.h>
21 #include "clk-id.h"
112 /* Tegra CPU clock and reset control regs */
595 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
596 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
597 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
[all …]
H A Dclk-tegra20.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
13 #include <linux/clk/tegra.h>
15 #include <dt-bindings/clock/tegra20-car.h>
18 #include "clk-id.h"
113 /* Tegra CPU clock and reset control regs */
444 { .dev_id = "tegra20-ac97", .dt_id = TEGRA20_CLK_AC97 },
445 { .dev_id = "tegra-apbdma", .dt_id = TEGRA20_CLK_APBDMA },
446 { .dev_id = "rtc-tegra", .dt_id = TEGRA20_CLK_RTC },
448 { .dev_id = "tegra-kbc", .dt_id = TEGRA20_CLK_KBC },
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/linux/drivers/gpu/drm/nouveau/include/nvif/
H A Dos.h1 /* SPDX-License-Identifier: MIT */
15 #include <linux/i2c-algo-bit.h>
17 #include <linux/io-mapping.h>
35 #include <soc/tegra/fuse.h>
36 #include <soc/tegra/pmc.h>
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
7 #include "tegra20-cpu-opp.dtsi"
8 #include "tegra20-cpu-opp-microvolt.dtsi"
21 stdout-path = "serial0:115200n8";
40 vdd-supply = <&hdmi_vdd_reg>;
41 pll-supply = <&hdmi_pll_reg>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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H A Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
25 stdout-path = "serial0:115200n8";
44 vdd-supply = <&hdmi_vdd_reg>;
45 pll-supply = <&hdmi_pll_reg>;
47 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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H A Dtegra20-tamonten.dtsi1 // SPDX-License-Identifier: GPL-2.0
15 stdout-path = "serial0:115200n8";
24 vdd-supply = <&hdmi_vdd_reg>;
25 pll-supply = <&hdmi_pll_reg>;
27 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
28 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
34 pinctrl-names = "default";
35 pinctrl-0 = <&state_default>;
144 pmc {
145 nvidia,pins = "pmc";
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H A Dtegra30-asus-nexus7-grouper-ti-pmic.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/gpio/gpio.h>
13 #interrupt-cells = <2>;
14 interrupt-controller;
15 wakeup-source;
17 ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
18 ti,system-power-controller;
19 ti,sleep-keep-ck32k;
20 ti,sleep-enable;
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H A Dtegra30-asus-nexus7-grouper-maxim-pmic.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/interrupt-controller/arm-gic.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/mfd/max77620.h>
14 #interrupt-cells = <2>;
15 interrupt-controller;
17 #gpio-cells = <2>;
18 gpio-controller;
20 system-power-controller;
22 pinctrl-names = "default";
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H A Dtegra20-asus-tf101.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
16 chassis-type = "convertible";
33 * pre-existing /chosen node to be available to insert the
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H A Dtegra20-harmony.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
18 stdout-path = "serial0:115200n8";
37 hdmi-supply = <&vdd_5v0_hdmi>;
38 vdd-supply = <&hdmi_vdd_reg>;
39 pll-supply = <&hdmi_pll_reg>;
41 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
42 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
48 pinctrl-names = "default";
[all …]
/linux/drivers/ata/
H A Dahci_tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <soc/tegra/fuse.h>
21 #include <soc/tegra/pmc.h>
25 #define DRV_NAME "tegra-ahci"
184 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra_ahci_handle_quirks() local
187 if (tegra->sata_aux_regs && !tegra->soc->supports_devslp) { in tegra_ahci_handle_quirks()
188 val = readl(tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
190 writel(val, tegra->sata_aux_regs + SATA_AUX_MISC_CNTL_1_0); in tegra_ahci_handle_quirks()
196 struct tegra_ahci_priv *tegra = hpriv->plat_data; in tegra124_ahci_init() local
208 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra124_ahci_init()
[all …]
/linux/include/uapi/linux/
H A Dserial_core.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
19 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
22 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
23 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
56 /* NVIDIA Tegra Combined UART */
80 /* SH-SCI */
123 /* SH-SCI */
147 /* SH-SCI */
156 /* TI OMAP-UART */
171 /* ARC (Synopsys) on-chip UART */
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/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra USB PHY
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
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