| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | ti,omap-remoteproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
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| H A D | ti,k3-dsp-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
14 that are used to offload some of the processor-intensive tasks or algorithms,
17 These processor sub-systems usually contain additional sub-modules like
19 controller, a dedicated local power/sleep controller etc. The DSP processor
20 cores in the K3 SoCs are usually either a TMS320C66x CorePac processor or a
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| H A D | ti,keystone-rproc.txt | 5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
10 a dedicated local power/sleep controller etc. The DSP processor core in
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
15 Each DSP Core sub-system is represented as a single DT node, and should also
17 or optional properties that enable the OS running on the host processor (ARM
18 CorePac) to perform the device management of the remote processor and to
19 communicate with the remote processor.
22 --------------------
25 - compatible: Should be one of the following,
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| H A D | ti,davinci-rproc.txt | 4 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
5 is used to offload some of the processor-intensive tasks or algorithms, for
8 The processor cores in the sub-system usually contain additional sub-modules
10 controller, a dedicated local power/sleep controller etc. The DSP processor
15 Each DSP Core sub-system is represented as a single DT node.
18 --------------------
21 - compatible: Should be one of the following,
22 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
24 - reg: Should contain an entry for each value in 'reg-names'.
27 the parent node's '#address-cells' and '#size-cells' values.
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| H A D | ti,k3-r5f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI K3 R5F processor subsystems
10 - Suman Anna <s-anna@ti.com>
13 The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14 processor subsystems/clusters (R5FSS). The dual core cluster can be used
20 AM64x SoCs do not support LockStep mode, but rather a new non-safety mode
21 called "Single-CPU" mode, where only Core0 is used, but with ability to use
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| H A D | ti,k3-m4f-rproc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,k3-m4f-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI K3 M4F processor subsystems
10 - Hari Nagalla <hnagalla@ti.com>
11 - Mathieu Poirier <mathieu.poirier@linaro.org>
17 home automation applications, may use the M4F core as a remote processor
20 $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
25 - ti,am64-m4fss
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| /linux/Documentation/devicetree/bindings/mailbox/ |
| H A D | ti,omap-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
15 external to the various processor subsystems and is connected on an
21 controller within a processor subsystem, and there can be more than one line
22 going to a specific processor's interrupt controller. The interrupt line
35 lines can also be routed to different processor sub-systems on DRA7xx as they
40 to different processor subsystems over a limited number of common interrupt
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| /linux/sound/soc/codecs/ |
| H A D | tscs454.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // tscs454.c -- TSCS454 ALSA SoC Audio driver
21 #include <sound/soc-dapm.h>
50 pll->id = id; in pll_init()
51 mutex_init(&pll->lock); in pll_init()
66 aif->id = id; in aif_init()
85 cache[((norm_addrs[i] + 1) * COEFF_SIZE) - 1] = 0x40; in init_coeff_ram_cache()
90 init_coeff_ram_cache(ram->cache); in coeff_ram_init()
91 mutex_init(&ram->lock); in coeff_ram_init()
103 status->streams |= mask; in set_aif_status_active()
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| /linux/Documentation/userspace-api/media/ |
| H A D | glossary.rst | 1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
52 **Digital Signal Processor**
58 **Field-programmable Gate Array**
63 See https://en.wikipedia.org/wiki/Field-programmable_gate_array.
72 together make a larger user-facing functional peripheral. For
80 **Inter-Integrated Circuit**
82 A multi-master, multi-slave, packet switched, single-ended,
84 like sub-device hardware components.
86 See http://www.nxp.com/docs/en/user-guide/UM10204.pdf.
108 **Image Signal Processor**
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| /linux/arch/arm/kernel/ |
| H A D | head-nommu.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-nommu.S
5 * Copyright (C) 1994-2002 Russell King
6 * Copyright (C) 2003-2006 Hyok S. Choi
8 * Common kernel startup code (non-paged MM)
16 #include <asm/asm-offsets.h>
25 * ---------------------------
28 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
31 * See linux/arch/arm/tools/mach-types for the complete list of machine
46 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
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| H A D | head-common.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm/kernel/head-common.S
5 * Copyright (C) 1994-2002 Russell King
18 #define OF_DT_MAGIC 0xedfe0dd0 /* 0xd00dfeed in big-endian */
71 * r0 = cp#15 control register (exc_ret for M-class)
74 * r9 = processor ID
97 sub r2, r2, r1
104 sub r2, r1, r0
112 str r9, [r0] @ Save processor ID
149 .size __mmap_switched_data, . - __mmap_switched_data
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| H A D | head.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1994-2002 Russell King
9 * Kernel startup code for all 32-bit CPUs
19 #include <asm/asm-offsets.h>
48 .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
69 sub \rd, \rd, #PG_DIR_SIZE
74 * ---------------------------
77 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
83 * See linux/arch/arm/tools/mach-types for the complete list of machine
87 * crap here - that's what the boot loader (or in extreme, well justified
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| /linux/Documentation/admin-guide/media/ |
| H A D | qcom_camss.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 ------------
25 ----------------------------------
30 - 2 / 3 CSIPHY modules. They handle the Physical layer of the CSI2 receivers.
32 - 2 / 4 CSID (CSI Decoder) modules. They handle the Protocol and Application
36 - ISPIF (ISP Interface) module. Handles the routing of the data streams from
38 - 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
48 -----------------------
52 - Input from camera sensor via CSIPHY;
53 - Generation of test input data by the TG in CSID;
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| /linux/Documentation/devicetree/bindings/clock/ |
| H A D | qcom,kpss-gcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
10 - Christian Marangi <ansuelsmth@gmail.com>
13 Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
15 to the kpss-gcc registers.
20 - enum:
21 - qcom,kpss-gcc-ipq8064
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| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | omap-ocp2scp.txt | 1 * OMAP OCP2SCP - ocp interface to scp interface
4 - compatible : Should be "ti,am437x-ocp2scp" for AM437x processor
5 Should be "ti,omap-ocp2scp" for all others
6 - reg : Address and length of the register set for the device
7 - #address-cells, #size-cells : Must be present if the device has sub-nodes
8 - ranges : the child address space are mapped 1:1 onto the parent address space
9 - ti,hwmods : must be "ocp2scp_usb_phy"
11 Sub-nodes:
12 All the devices connected to ocp2scp are described using sub-node to ocp2scp
15 compatible = "ti,omap-ocp2scp";
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| /linux/arch/sparc/kernel/ |
| H A D | head_64.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
25 #include <asm/processor.h>
93 * SILO can invoke us with 32-bit address masking enabled,
125 .asciz "call-method"
133 .asciz "SUNW,set-trap-table"
137 .asciz "SUNW,UltraSPARC-T"
139 .asciz "SPARC-"
141 .asciz "SPARC64-X"
169 mov (1b - prom_peer_name), %l1
170 sub %l0, %l1, %l1
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| /linux/drivers/crypto/ccp/ |
| H A D | sp-dev.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD Secure Processor driver
5 * Copyright (C) 2017-2018 Advanced Micro Devices, Inc.
22 #include "ccp-dev.h"
23 #include "sp-dev.h"
29 MODULE_DESCRIPTION("AMD Secure Processor driver");
31 /* List of SPs, SP count, read-write access lock, and access functions
39 /* Ever-increasing value to produce unique unit numbers */
48 list_add_tail(&sp->entry, &sp_units); in sp_add_device()
59 list_del(&sp->entry); in sp_del_device()
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| /linux/arch/nios2/kernel/ |
| H A D | head.S | 7 * Based on head.S for Altera's Excalibur development board with nios processor
20 #include <asm/processor.h>
23 #include <asm/asm-offsets.h>
24 #include <asm/asm-macros.h>
27 * ZERO_PAGE is a special page that is used for zero-initialized
48 * Input(s): passed from u-boot
49 * r4 - Optional pointer to a board information structure.
50 * r5 - Optional pointer to the physical starting address of the init RAM
52 * r6 - Optional pointer to the physical ending address of the init RAM
54 * r7 - Optional pointer to the physical starting address of any kernel
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| /linux/include/linux/ |
| H A D | processor.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Misc low level processor primitives */
6 #include <asm/processor.h>
9 * spin_begin is used before beginning a busy-wait loop, and must be paired
17 * Violations of these guidelies will not cause a bug, but may cause sub
23 * Detection of resource owner and decision to spin or sleep or guest-yield
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| /linux/arch/sh/include/asm/ |
| H A D | spinlock-llsc.h | 1 /* SPDX-License-Identifier: GPL-2.0
3 * include/asm-sh/spinlock-llsc.h
12 #include <asm/processor.h>
18 #define arch_spin_is_locked(x) ((x)->lock <= 0)
22 * on the local processor, one does not.
41 : "r" (&lock->lock) in arch_spin_lock()
56 : "r" (&lock->lock) in arch_spin_unlock()
74 : "r" (&lock->lock) in arch_spin_trylock()
82 * Read-write spinlocks, allowing multiple readers but only one writer.
85 * writers. For those circumstances we can "mix" irq-safe locks - any writer
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| /linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,coresight-dummy-source.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-source.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
19 there would be Coresight source trace components on sub-processor which
20 are connected to AP processor via debug bus. For these devices, a dummy driver
30 - Mike Leach <mike.leach@linaro.org>
31 - Suzuki K Poulose <suzuki.poulose@arm.com>
32 - James Clark <james.clark@linaro.org>
33 - Mao Jinlong <quic_jinlmao@quicinc.com>
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| /linux/Documentation/gpu/ |
| H A D | komeda-kms.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 The drm/komeda driver supports the Arm display processor D71 and later products,
23 -----
30 ------
39 -------------------
41 frame. its output frame can be fed into post image processor for showing it on
47 --------------------------
51 Post image processor (improc)
52 -----------------------------
53 Post image processor adjusts frame data like gamma and color space to fit the
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| /linux/arch/arm/nwfpe/ |
| H A D | entry.S | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
17 sub r4, r5, #4
24 strb r8, [r10, #TSK_USED_MATH] @ set current->used_math
64 #include <asm/asm-offsets.h>
68 mov r4, lr @ save the failure-return addresses
118 @ Check whether the instruction is a co-processor instruction.
119 @ If yes, we need to call the relevant co-processor handler.
131 sub r4, r4, #4 @ ARM instruction at user PC - 4
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| /linux/tools/power/x86/x86_energy_perf_policy/ |
| H A D | x86_energy_perf_policy.8 | 1 .\" This page Copyright (C) 2010 - 2015 Len Brown <len.brown@intel.com>
5 x86_energy_perf_policy \- Manage Energy vs. Performance Policy via x86 Model Specific Registers
10 .RB "scope: \-\-cpu\ cpu-list | \-\-pkg\ pkg-list"
12 .RB "cpu-list, pkg-list: # | #,# | #-# | all"
14 .RB "field: \-\-all | \-\-epb | \-\-hwp-epp | \-\-hwp-min | \-\-hwp-max | \-\-hwp-desired"
16 .RB "other: (\-\-force | \-\-hwp-enable | \-\-turbo-enable) value)"
18 .RB "value: # | default | performance | balance-performance | balance-power | power"
21 displays and updates energy-performance policy settings specific to
23 updates, no matter if the Linux cpufreq sub-system is enabled or not.
27 such as how aggressively the hardware enters and exits CPU idle states (C-states)
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| /linux/arch/sh/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
78 The SuperH is a RISC processor targeted for use in embedded systems
81 <http://www.linux-sh.org/>.
152 # Processor families
214 prompt "Processor sub-type selection"
217 # Processor subtypes
220 # SH-2 Processor Support
223 bool "Support SH7619 processor"
228 bool "Support J2 processor"
233 # SH-2A Processor Support
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