| /illumos-gate/usr/src/cmd/pginfo/ |
| H A D | pginfo.pl | 28 # pginfo - tool for displaying Processor Group information
53 # 0 System 0-7
72 # 2 Invalid command-line options were specified.
91 my $do_cpulist; # -C - Show CPU IDs
92 my $do_cpus; # -c - Treat args as CPU IDs
93 my $do_physical; # -p - Show physical relationships
94 my $do_sharing_only; # -S - Only show sharing relationships
95 my $do_tree; # -T - Show ASCII tree
96 my $do_usage; # -h - Show usage
97 my $do_version; # -V - Show version
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| /illumos-gate/usr/src/cmd/svc/shell/ |
| H A D | net_include.sh | 42 while [ $# -ge 1 ]; do
56 if [ $err -ne 0 ]; then
89 set -- $1
105 set -- $1
108 if [ -z "$2" ]; then
123 physical_comp $1 $2 && [ `get_logical $1` -eq `get_logical $2` ]
148 while [ $# -gt 0 ]; do
159 # Return the IPMP meta-interface name for the group, if it exists.
163 /sbin/ipmpstat -gP -o groupname,group | while IFS=: read name ifname; do
176 # specified group, or non-zero otherwise.
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| /illumos-gate/usr/src/uts/sun4/ml/ |
| H A D | swtch.S | 44 * a thread can only run on one processor at a time. there
46 * processor is capable of being dispatched by another processor.
49 * are the same, resume() on one processor will spin on the incoming
50 * thread until resume() on the other processor has finished with
69 save %sp, -SA(MINFRAME), %sp ! save ins and locals
84 ! This handles floating-point state saving.
142 ldn [%i0 + T_PROCP], %i3 ! delay slot - get proc pointer
144 mov THREAD_REG, %o0 ! delay - arg = thread pointer
146 ldn [THREAD_REG + T_PROCP], %i2 ! load old curproc - for mmu
153 sub %o1, SA(MINFRAME), %sp ! save room for ins and locals
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| H A D | proc_init.S | 45 * Processor initialization
77 sub %g1, SA(KFPUSIZE+GSR_SIZE), %g2
79 sub %g2, %g3, %o2
80 sub %o2, SA(MINFRAME) + STACK_BIAS, %sp
85 sub %g0, 1, THREAD_REG ! catch any curthread acceses
88 ! ASI_MEMCNTL. To avoid Olympus-C and Jupiter sTLB errata (strands with
90 ! reference to non-nucleus memory. An early hook is added to perform
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| /illumos-gate/usr/src/cmd/pgstat/ |
| H A D | pgstat.pl | 28 # pgstat - tool for displaying Processor Group statistics
53 # 0 System 0-7
58 # DEFAULT_INTERVAL - interval in seconds between snapshot if none is specified
59 # DEFAULT_COUNT - Number of iterations if none is specified
60 # HWLOAD_UNKNOWN - Value that we use to represent unknown hardware load
61 # HWLOAD_UNDEF - Value that we use to represent undefined hardware load
69 HWLOAD_UNKNOWN => -1,
70 HWLOAD_UNDEF => -2,
90 # 2 Invalid command-line options were specified.
99 # Valid sort keys for -s and -S options
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| /illumos-gate/usr/src/uts/sun4u/cpu/ |
| H A D | spitfire_asm.S | 69 sub tmp3, tmp1, tmp2 ;\
75 sub tmp2, tmp1, tmp2 ;\
89 sub tmp3, tmp1, tmp3 ;\
93 bz,pn %icc, 5f /* branch if no valid sub-blocks */ ;\
103 sub tmp3, tmp1, tmp3 ;\
115 sub tmp3, tmp1, arg2 ;\
119 bz,pn %icc, 5f /* br if no valid sub-blocks */ ;\
129 sub arg2, tmp1, arg2 ;\
148 sub tmp2, tmp1, tmp2; \
154 sub tmp2, tmp1, tmp2; \
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| H A D | opl_olympus_asm.S | 25 * Assembly code support for the Olympus-C module
57 * arg3 = ecache flush address - Not used for olympus-C
65 * SPARC64-VI MMU and Cache operations.
106 * Secondary context cannot be used for SPARC64-VI IMMU.
113 ldub [%o1 + SFMMU_CEXT], %o4 ! %o4 = sfmmup->sfmmu_cext
154 * x-trap to flush page from tlb and tsb
156 * %g1 = vaddr, zero-extended on 32-bit kernel
180 ldub [%g2 + SFMMU_CEXT], %g4 ! %g4 = sfmmup->cext
199 * x-trap to flush pgcnt MMU_PAGESIZE pages from tlb
201 * %g1 = vaddr, zero-extended on 32-bit kernel
[all …]
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| H A D | us3_common_asm.S | 75 sub tmp3, tmp1, tmp2 ;\
81 sub tmp2, tmp1, tmp2 ;\
95 sub tmp3, tmp1, tmp3 ;\
102 sub tmp3, tmp1, tmp3 ;\
114 sub tmp3, tmp1, arg2 ;\
118 bz,pn %icc, 5f /* br if no valid sub-blocks */ ;\
128 sub arg2, tmp1, arg2 ;\
159 sub tmp2, tmp1, tmp2; \
165 sub tmp2, tmp1, tmp2; \
219 ldub [%o1 + SFMMU_CEXT], %o4 ! %o4 = sfmmup->sfmmu_cext
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| /illumos-gate/usr/src/uts/common/sys/ |
| H A D | pci.h | 47 #define PCI_CONF_SUBCLASS 0xA /* sub-class code, 1 byte */
182 #define PCI_STAT_FBBC 0x80 /* Fast Back-to-Back Capable */
209 #define PCI_CLASS_NONE 0x0 /* class code for pre-2.0 devices */
220 #define PCI_CLASS_PROCESSOR 0xb /* Processor class */
229 * PCI Sub-class codes - base class 0x0 (no new devices should use this code).
235 * PCI Sub-class codes - base class 0x1 (mass storage controllers)
245 #define PCI_MASS_NVME 0x8 /* Non-Volatile memory controller */
278 * PCI Sub-class codes - base class 0x2 (Network controllers)
290 * PCI Sub-class codes - base class 03 (display controllers)
304 * PCI Sub-class codes - base class 0x4 (multi-media devices)
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| H A D | mac_soft_ring.h | 38 #include <sys/processor.h>
103 processorid_t s_ring_cpuid; /* processor to bind to */
149 * packets will get buffered with no flow-control
259 * Rx-side notes:
287 * default behavior of srs though is to act as a pass-thru. The queues
340 * They are common to both Rx- and Tx-side.
350 /* Attribute specific drain func (BW ctl vs non-BW ctl) */
374 processorid_t srs_worker_cpuid; /* processor to bind to */
376 processorid_t srs_poll_cpuid; /* processor to bind to */
387 * type flags - combination allowed to process and drain the queue
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| /illumos-gate/usr/src/uts/intel/sys/amdzen/ |
| H A D | smn.h | 28 * ------------------------
30 * ------------------------
45 * matters, some functional units have multiple smaller sub-units that decode
47 * mask describing the sub-unit's registers may not be contiguous. To keep
48 * software relatively simple, we generally treat sub-units and parent units the
55 * sub-units, registers with many instances whose locations are computed in
60 * processor family (see cpuid.c) or other collection and may require their own
63 * are they generally self-discoverable. Each functional unit may be present or
65 * Zen product range. Therefore, at this time most per-unit headers are
66 * intended for use only by code that will execute on a specific processor
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| /illumos-gate/usr/src/uts/common/xen/public/ |
| H A D | platform.h | 4 * Hardware platform operations. Intended for use by domain-0 kernel.
24 * Copyright (c) 2002-2006, K Fraser
49 * Request memory range (@mfn, @mfn+@nr_mfns-1) to have type @type.
50 * On x86, @type is an architecture-defined MTRR memory type.
53 * (x86-specific).
69 * Tear down an existing memory-range type. If @handle is remembered then it
73 * (x86-specific).
84 /* Read current type of an MTRR (x86-specific). */
107 #define QUIRK_NOIRQBALANCING 1 /* Do not restrict IO-APIC RTE targets */
108 #define QUIRK_IOAPIC_BAD_REGSEL 2 /* IO-APIC REGSEL forgets its value */
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| /illumos-gate/usr/src/uts/sun4v/ml/ |
| H A D | mach_proc_init.S | 28 * sun4v processor initialization
45 * %o0 - hcall specified arg (cpuid)
46 * %i0 - real memory base
47 * %i1 - memory size
62 wrpr %g0, MAXWIN - 2, %cansave
63 wrpr %g0, MAXWIN - 2, %cleanwin
98 sub %g2, %g1, %g2
138 sub %l2, 1, %l2 ! decrement counter
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| /illumos-gate/usr/src/uts/sun4v/sys/ |
| H A D | machclock.h | 61 sub scr1, scr2, scr2; \
77 * So, always use the constant-frequency %stick on sun4v.
109 sub scr1, scr2, scr2; \
142 * If the kernel variable passed in as 'use_stick' is non-zero,
144 * read the %tick counter. Note the label-less branches.
173 sub scr1, scr2, scr2; \
181 sub in, scr1, scr1; \
191 * on a CMT processor.
198 * Constants used to convert hi-res timestamps into nanoseconds
203 * At least 62.5 MHz, for faster %tick-based systems.
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| /illumos-gate/usr/src/data/perfmon/TGL/ |
| H A D | tigerlake_core_v1.00.json | 6 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
7 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
73 …ent stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. Th…
94 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
95 …processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-…
336 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
337 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
359 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
447 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
469 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
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| /illumos-gate/usr/src/uts/intel/sys/ |
| H A D | x86_archext.h | 31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
45 #include <sys/processor.h>
59 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
68 /* 0x400 - reserved */
75 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
76 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
78 /* 0x100000 - reserved */
85 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
97 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
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| /illumos-gate/usr/src/uts/sparc/v9/ml/ |
| H A D | sparcv9_subr.S | 32 * architecture-dependent routines change, the routines should be moved
33 * from this file into the respective ../`arch -k`/subr.s file.
56 * Macro to raise processor priority level.
57 * Avoid dropping processor priority if already at high level.
58 * Also avoid going below CPU->cpu_base_spl, which could've just been set by
59 * a higher-level interrupt thread that just blocked.
79 * Macro to raise processor priority level to level >= DISP_LEVEL.
80 * Doesn't require comparison to CPU->cpu_base_spl.
96 * Avoid dropping the priority below CPU->cpu_base_spl.
114 * Doesn't require comparison to CPU->cpu_base_spl.
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| /illumos-gate/usr/src/cmd/fm/modules/common/fdd-msg/ |
| H A D | fdd_msg.c | 29 * fdd-msg module is called once when fmd starts up. It does the following
32 * 1. If it's on a x86 platform, fdd-msg module sends fdd running on service
33 * processor a message (ILOM) which indicates the Solaris host FMA capability.
35 * of ILOM using the IPMI Sun OEM core tunnel command. The sub-command is
41 * 2. If it's on a Sparc platform, fdd-msg module just exit for now.
85 return (-1); in check_sunoem()
88 return (-2); in check_sunoem()
104 return (-1); in fma_cap_cpu_info()
107 return (-1); in fma_cap_cpu_info()
112 return (-1); in fma_cap_cpu_info()
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| /illumos-gate/usr/src/common/crypto/arcfour/amd64/ |
| H A D | arcfour-x86_64.pl | 10 # 2.22x RC4 tune-up:-) It should be noted though that my hand [as in
11 # "hand-coded assembler"] doesn't stand for the whole improvement
23 # results in even higher performance gain of 3.3x:-) At least on
24 # Opteron... For reference, 1x in this case is RC4_CHAR C-code
36 # P4 EM64T core appears to be "allergic" to 64-bit inc/dec. Replacing
37 # those with add/sub results in 50% performance improvement of folded
41 # performance by >30% [unlike P4 32-bit case that is]. But this is
44 # as my IA-64 implementation. On Opteron this resulted in modest 5%
46 # achieves respectful 432MBps on 2.8GHz processor now. For reference.
47 # If executed on Xeon, current RC4_CHAR code-path is 2.7x faster than
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| /illumos-gate/usr/src/lib/libc/amd64/gen/ |
| H A D | strlen.S | 28 * strlen - calculate the length of string
48 * Unaligned case. Round down to 16-byte boundary before comparing
62 sub %rcx, %rsi /* no null, adjust to next 16-byte boundary */
96 * Check to see if BSF is fast on this processor. If not, use a different
102 lea -16(%rdi, %rsi), %rax /* calculate exact offset */
112 lea -16(%rdi, %rsi), %rax
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| /illumos-gate/usr/src/uts/intel/io/amdzen/ |
| H A D | zen_umc.h | 65 #define ZEN_UMC_MAX_DRAM_OFFSET (ZEN_UMC_MAX_CS_RULES - 1)
110 * This is the number of memory P-states that the UMC supports. This appears to
112 * current P-state, it is hard to really know when these transitions occur. We
285 * purposes. It basically means that there is at least one chip-select
288 * and being usable. This likely needs to be re-evaluated when we
298 * chip-select decoding register is enabled.
305 * is activated by a 'chip-select' signal on a DIMM (e.g. CS_L[1:0]). In a given
306 * channel, AMD always has two instances of a 'chip-select' data structure.
309 * used to determine which of the additional chip and chip-select signals to
311 * structures. To match AMD terminology we call these a 'chip-select' or
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| /illumos-gate/usr/src/cmd/hal/hald/solaris/ |
| H A D | sysevent.c | 5 * Copyright 2022 Carsten Grzemba <grzemba@contac-dt.de>
279 HAL_INFO (("sysevent: class=%s, sub=%s", class, subclass)); in sysevent_iochannel_data()
310 HAL_DEBUG (("In %s, AP_ID-> %s, Hint-> %s", class, in sysevent_iochannel_data()
520 * Find the CPU's that are DR removed. For each "processor" device in in sysevent_dr_remove_cpu()
535 * Iterate through the HAL device list to get the processor devices in sysevent_dr_remove_cpu()
538 iter = gdl->devices; in sysevent_dr_remove_cpu()
541 d = HAL_DEVICE (iter->data); in sysevent_dr_remove_cpu()
543 if (!hal_device_has_property (d, "processor.number")) { in sysevent_dr_remove_cpu()
544 iter = iter->next; in sysevent_dr_remove_cpu()
548 cpu_id = hal_device_property_get_int (d, "processor.number"); in sysevent_dr_remove_cpu()
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| /illumos-gate/usr/src/data/perfmon/ICL/ |
| H A D | icelake_core_v1.09.json | 6 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
7 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve…
76 …ent stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. Th…
98 …"BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - archit…
99 …processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-…
351 …"BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store …
352 …"PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or …
375 …icDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped du…
467 …y executing divide or square root operations. Accounts for integer and floating-point operations.",
513 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
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| /illumos-gate/usr/src/cmd/acpi/common/ |
| H A D | dmtbinfo2.c | 3 * Module Name: dmtbinfo2 - Table info for non-AML tables
11 * Some or all of this work - Copyright (c) 1999 - 2018, Intel Corp.
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
108 * any of its subsidiaries will export/re-export any technical data, process,
130 * 3. Neither the names of the above-listed copyright holders nor the names
157 /* This module used for application-level code only */
165 * - Add the C table definition to the actbl1.h or actbl2.h header.
166 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below.
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| /illumos-gate/usr/src/lib/libdwarf/common/ |
| H A D | config.h | 7 /* Define to one of `_getb67', `GETB67', `getb67' for Cray-2 and Cray-YMP
142 /* Define to the sub-directory where libtool stores uninstalled libraries. */
145 /* Define to 1 if your C compiler doesn't accept -c and -o together. */
152 #define PACKAGE_BUGREPORT "libdwarf-list -at- linuxmail -dot- org"
183 /* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most
|