Lines Matching +full:sub +full:- +full:processor
31 * Copyright 2012 Jens Elkner <jel+illumos@cs.uni-magdeburg.de>
32 * Copyright 2012 Hans Rosenfeld <rosenfeld@grumpf.hope-2000.org>
45 #include <sys/processor.h>
59 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */
68 /* 0x400 - reserved */
75 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
76 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */
78 /* 0x100000 - reserved */
85 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */
97 #define CPUID_INTC_ECX_DTES64 0x00000004 /* 64-bit DS area */
99 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */
106 /* 0x00000800 - reserved */
111 /* 0x00010000 - reserved */
112 #define CPUID_INTC_ECX_PCID 0x00020000 /* process-context ids */
133 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */
142 /* 0x00000400 - sysc on K6m6 */
150 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */
151 /* 0x00040000 - reserved */
152 /* 0x00080000 - reserved */
153 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */
154 /* 0x00200000 - reserved */
161 /* 0x10000000 - reserved */
174 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */
184 /* 0x00004000 - reserved */
186 #define CPUID_AMD_ECX_FMA4 0x00010000 /* AMD: 4-operand FMA support */
187 /* 0x00020000 - reserved */
188 /* 0x00040000 - reserved */
190 /* 0x00100000 - reserved */
195 /* 0x02000000 - reserved */
200 /* 0x40000000 - reserved */
201 /* 0x80000000 - reserved */
236 * AMD Encrypted Memory Capabilities -- 0x8000_001F
239 * %edx is the minimum ASID value for SEV enabled, SEV-ES disabled guests
245 #define CPUID_AMD_8X1F_EAX_IBSVGC (1 << 19) /* IBS Virt. for SEV-ES */
250 #define CPUID_AMD_8X1F_EAX_DBGSWP (1 << 14) /* Debug state for SEV-ES */
268 #define CPUID_AMD_8X1F_EBX_CBIT(r) bitx32(r, 5, 0) /* C-bit loc in PTE */
271 * AMD Platform QoS Extended Features -- 0x8000_0020
276 * AMD Extended Feature 2 -- 0x8000_0021
290 * AMD Extended Performance Monitoring and Debug -- 0x8000_0022
301 * AMD Secure Multi-key Encryption -- 0x8000_00023
303 #define CPUID_AMD_8X23_EAX_MEMHMK (1 << 0) /* Secure Host Multi-Key Mem */
308 * AMD Extended CPU Topology -- 0x8000_0026
317 * processor specific.
319 * %edx is the entire extended APIC ID of the logical processor we're on.
341 * space that we previously for non-Intel implementors to use.
354 #define CPUID_INTC_EAX_ARAT 0x00000004 /* APIC-Timer-Always-Running */
377 /* bits 1-2 are reserved */
383 * requires us to specify both a leaf in %eax and a sub-leaf in %ecx. To deal
384 * with the potential use of additional sub-leaves in the future, we now
385 * specifically label the EBX features with their leaf and sub-leaf.
412 #define CPUID_INTC_EBX_7_0_PTRACE 0x02000000 /* Processor Trace */
442 #define CPUID_INTC_ECX_7_0_LA57 0x00010000 /* 57-bit paging */
443 /* bits 17-21 are the value of MAWAU */
465 /* bits 0-1 are reserved */
470 /* bits 6-7 are reserved */
474 /* bits 11-13 are reserved */
497 /* bits 0-3 are reserved */
500 /* bits 6-9 are reserved */
501 #define CPUID_INTC_EAX_7_1_ZL_MOVSB 0x00000400 /* zero-length MOVSB */
504 /* bits 13-21 are reserved */
506 /* bits 23-25 are reserved */
508 /* bits 27-31 are reserved */
514 * when the sub-leaf in %ecx == 1. We label these using the same convention as
546 /* Intel P4 (pre-Prescott, non P4 M) */
790 * Older (pre-F15h) CPUs exposed a set of 4 CPU performance counters, along with
793 * original 4 counters aliasing onto the new ones, entries 0-3)
832 #define AMD_PERF_EVTSEL_HG_GUEST 0x10000000000 /* Guest-only */
833 #define AMD_PERF_EVTSEL_HG_HOST 0x20000000000 /* Host-only */
842 * section 7.9.4 ("Top of Memory"), states that "a given processor may implement
843 * fewer than the architecturally-defined number of physical address bits." It
865 * PAT0 Write-Back
866 * PAT1 Write-Through
867 * PAT2 Unchacheable-
869 * PAT4 Write-Back
870 * PAT5 Write-Through
871 * PAT6 Write-Combine
1001 * Intel Deep C-State invariant TSC in leaf 0x80000007.
1081 * processor families and microarchitecture families relate to cpuid families,
1105 * chiprev/processor family changed with it. The ancient amd_opteron and mc-amd
1107 * 0x10. amdzen_umc wants the processor family, in part because AMD's
1109 * discerning anything about the processor. That also tied into the way
1113 * Because there are other consumers of the processor family, it no longer made
1114 * sense for amdzen to derive the processor family from the cpuid family/model
1129 * that, processor family and cpuid family were effectively the same, because
1385 * attempting to capture every possible fine-grained detail here; to the extent
1553 * Definitions for Intel processor models. These are all for Family 6
1685 * that all of the processor's normal logic and tracking of the xsave state is
1715 * These functions are all used to perform various side-channel mitigations.