xref: /illumos-gate/usr/src/data/perfmon/TGL/tigerlake_core_v1.00.json (revision 43449cdcd0600512dd862537f2cf014140dd0844)

[
  {
    "EventCode": "0x00",
    "UMask": "0x01",
    "EventName": "INST_RETIRED.ANY",
    "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
    "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
    "Counter": "32",
    "PEBScounters": "32",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x00",
    "UMask": "0x01",
    "EventName": "INST_RETIRED.PREC_DIST",
    "BriefDescription": "Precise instruction retired event with a reduced effect of PEBS shadow in IP distribution",
    "PublicDescription": "A version of INST_RETIRED that allows for a more unbiased distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR) feature to mitigate some bias in how retired instructions get sampled. Use on Fixed Counter 0.",
    "Counter": "32",
    "PEBScounters": "32",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x00",
    "UMask": "0x02",
    "EventName": "CPU_CLK_UNHALTED.THREAD",
    "BriefDescription": "Core cycles when the thread is not in halt state",
    "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
    "Counter": "33",
    "PEBScounters": "33",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x00",
    "UMask": "0x03",
    "EventName": "CPU_CLK_UNHALTED.REF_TSC",
    "BriefDescription": "Reference cycles when the core is not in halt state.",
    "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
    "Counter": "34",
    "PEBScounters": "34",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x00",
    "UMask": "0x04",
    "EventName": "TOPDOWN.SLOTS",
    "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
    "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
    "Counter": "35",
    "PEBScounters": "35",
    "SampleAfterValue": "10000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x03",
    "UMask": "0x02",
    "EventName": "LD_BLOCKS.STORE_FORWARD",
    "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
    "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x03",
    "UMask": "0x08",
    "EventName": "LD_BLOCKS.NO_SR",
    "BriefDescription": "The number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
    "PublicDescription": "Counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x07",
    "UMask": "0x01",
    "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
    "BriefDescription": "False dependencies in MOB due to partial compare on address.",
    "PublicDescription": "Counts the number of times a load got blocked due to false dependencies in MOB due to partial compare on address.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x02",
    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
    "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
    "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x04",
    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
    "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
    "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data loads. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x0E",
    "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
    "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
    "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x10",
    "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
    "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
    "PublicDescription": "Counts the number of page walks outstanding for a demand load in the PMH (Page Miss Handler) each cycle.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x10",
    "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
    "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
    "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a demand load.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x08",
    "UMask": "0x20",
    "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
    "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
    "PublicDescription": "Counts loads that miss the DTLB (Data TLB) and hit the STLB (Second level TLB).",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0D",
    "UMask": "0x01",
    "EventName": "INT_MISC.RECOVERY_CYCLES",
    "BriefDescription": "Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
    "PublicDescription": "Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "500009",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0d",
    "UMask": "0x03",
    "EventName": "INT_MISC.ALL_RECOVERY_CYCLES",
    "BriefDescription": "Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
    "PublicDescription": "Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0d",
    "UMask": "0x10",
    "EventName": "INT_MISC.UOP_DROPPING",
    "BriefDescription": "TMA slots where uops got dropped",
    "PublicDescription": "Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0d",
    "UMask": "0x80",
    "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES",
    "BriefDescription": "Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
    "PublicDescription": "Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "500009",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0E",
    "UMask": "0x01",
    "EventName": "UOPS_ISSUED.ANY",
    "BriefDescription": "Uops that RAT issues to RS",
    "PublicDescription": "Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x0E",
    "UMask": "0x01",
    "EventName": "UOPS_ISSUED.STALL_CYCLES",
    "BriefDescription": "Cycles when RAT does not issue Uops to RS for the thread",
    "PublicDescription": "Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x14",
    "UMask": "0x09",
    "EventName": "ARITH.DIVIDER_ACTIVE",
    "BriefDescription": "Cycles when divide unit is busy executing divide or square root operations.",
    "PublicDescription": "Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x22",
    "EventName": "L2_RQSTS.RFO_MISS",
    "BriefDescription": "RFO requests that miss L2 cache",
    "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x24",
    "EventName": "L2_RQSTS.CODE_RD_MISS",
    "BriefDescription": "L2 cache misses when fetching instructions",
    "PublicDescription": "Counts L2 cache misses when fetching instructions.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x28",
    "EventName": "L2_RQSTS.SWPF_MISS",
    "BriefDescription": "SW prefetch requests that miss L2 cache.",
    "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0x3f",
    "EventName": "L2_RQSTS.MISS",
    "BriefDescription": "All requests that miss L2 cache",
    "PublicDescription": "Counts all requests that miss L2 cache.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xc2",
    "EventName": "L2_RQSTS.RFO_HIT",
    "BriefDescription": "RFO requests that hit L2 cache",
    "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xc4",
    "EventName": "L2_RQSTS.CODE_RD_HIT",
    "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
    "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xc8",
    "EventName": "L2_RQSTS.SWPF_HIT",
    "BriefDescription": "SW prefetch requests that hit L2 cache.",
    "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. This event accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xE2",
    "EventName": "L2_RQSTS.ALL_RFO",
    "BriefDescription": "RFO requests to L2 cache",
    "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x24",
    "UMask": "0xE4",
    "EventName": "L2_RQSTS.ALL_CODE_RD",
    "BriefDescription": "L2 code requests",
    "PublicDescription": "Counts the total number of L2 code requests.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x28",
    "UMask": "0x07",
    "EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
    "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
    "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0.  This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x28",
    "UMask": "0x18",
    "EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
    "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
    "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1.  This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x28",
    "UMask": "0x20",
    "EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
    "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
    "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture).  This includes high current AVX 512-bit instructions.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x32",
    "UMask": "0x01",
    "EventName": "SW_PREFETCH_ACCESS.NTA",
    "BriefDescription": "Number of PREFETCHNTA instructions executed.",
    "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x32",
    "UMask": "0x02",
    "EventName": "SW_PREFETCH_ACCESS.T0",
    "BriefDescription": "Number of PREFETCHT0 instructions executed.",
    "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x32",
    "UMask": "0x04",
    "EventName": "SW_PREFETCH_ACCESS.T1_T2",
    "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
    "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x32",
    "UMask": "0x08",
    "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
    "BriefDescription": "Number of PREFETCHW instructions executed.",
    "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3C",
    "UMask": "0x00",
    "EventName": "CPU_CLK_UNHALTED.THREAD_P",
    "BriefDescription": "Thread cycles when thread is not in halt state",
    "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3c",
    "UMask": "0x01",
    "EventName": "CPU_CLK_UNHALTED.REF_XCLK",
    "BriefDescription": "Core crystal clock cycles when the thread is unhalted.",
    "PublicDescription": "Counts core crystal clock cycles when the thread is unhalted.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "25003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3C",
    "UMask": "0x02",
    "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
    "BriefDescription": "Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
    "PublicDescription": "Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "25003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x3c",
    "UMask": "0x08",
    "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED",
    "BriefDescription": "Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
    "PublicDescription": "This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x48",
    "UMask": "0x01",
    "EventName": "L1D_PEND_MISS.PENDING",
    "BriefDescription": "Number of L1D misses that are outstanding",
    "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x48",
    "UMask": "0x01",
    "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
    "BriefDescription": "Cycles with L1D load Misses outstanding.",
    "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x48",
    "UMask": "0x02",
    "EventName": "L1D_PEND_MISS.FB_FULL",
    "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
    "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x48",
    "UMask": "0x02",
    "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
    "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.",
    "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "1",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x48",
    "UMask": "0x04",
    "EventName": "L1D_PEND_MISS.L2_STALL",
    "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
    "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x02",
    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
    "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
    "PublicDescription": "Counts completed page walks  (4K sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x04",
    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
    "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
    "PublicDescription": "Counts completed page walks  (2M/4M sizes) caused by demand data stores. This implies address translations missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x0E",
    "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
    "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
    "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x10",
    "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
    "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
    "PublicDescription": "Counts the number of page walks outstanding for a store in the PMH (Page Miss Handler) each cycle.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x10",
    "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
    "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
    "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a store.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x49",
    "UMask": "0x20",
    "EventName": "DTLB_STORE_MISSES.STLB_HIT",
    "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
    "PublicDescription": "Counts stores that miss the DTLB (Data TLB) and hit the STLB (2nd Level TLB).",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x4c",
    "UMask": "0x01",
    "EventName": "LOAD_HIT_PREFETCH.SWPF",
    "BriefDescription": "Counts the number of demand load dispatches that hit L1D fill buffer (FB) allocated for software prefetch.",
    "PublicDescription": "Counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by ASM (Assembly File) inspection of the nearby instructions.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x51",
    "UMask": "0x01",
    "EventName": "L1D.REPLACEMENT",
    "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
    "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x54",
    "UMask": "0x01",
    "EventName": "TX_MEM.ABORT_CONFLICT",
    "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address",
    "PublicDescription": "Counts the number of times a TSX line had a cache conflict.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x54",
    "UMask": "0x02",
    "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
    "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional writes.",
    "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional writes.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x54",
    "UMask": "0x80",
    "EventName": "TX_MEM.ABORT_CAPACITY_READ",
    "BriefDescription": "Speculatively counts the number of TSX aborts due to a data capacity limitation for transactional reads",
    "PublicDescription": "Speculatively counts the number of Transactional Synchronization Extensions (TSX) aborts due to a data capacity limitation for transactional reads",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5d",
    "UMask": "0x02",
    "EventName": "TX_EXEC.MISC2",
    "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed inside a transactional region",
    "PublicDescription": "Counts Unfriendly TSX abort triggered by a vzeroupper instruction.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5d",
    "UMask": "0x04",
    "EventName": "TX_EXEC.MISC3",
    "BriefDescription": "Number of times an instruction execution caused the transactional nest count supported to be exceeded",
    "PublicDescription": "Counts Unfriendly TSX abort triggered by a nest count that is too deep.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5E",
    "UMask": "0x01",
    "EventName": "RS_EVENTS.EMPTY_CYCLES",
    "BriefDescription": "Cycles when Reservation Station (RS) is empty for the thread",
    "PublicDescription": "Counts cycles during which the reservation station (RS) is empty for this logical processor. This is usually caused when the front-end pipeline runs into stravation periods (e.g. branch mispredictions or i-cache misses)",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x5E",
    "UMask": "0x01",
    "EventName": "RS_EVENTS.EMPTY_END",
    "BriefDescription": "Counts end of periods where the Reservation Station (RS) was empty.",
    "PublicDescription": "Counts end of periods where the Reservation Station (RS) was empty. Could be useful to closely sample on front-end latency issues (see the FRONTEND_RETIRED event of designated precise events)",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "1",
    "EdgeDetect": "1",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x01",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
    "BriefDescription": "Demand Data Read transactions pending for off-core. Highly correlated.",
    "PublicDescription": "Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the core.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x01",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
    "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
    "PublicDescription": "Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x01",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
    "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
    "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "6",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x04",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
    "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
    "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x04",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
    "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
    "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x08",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
    "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
    "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x60",
    "UMask": "0x08",
    "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
    "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
    "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x63",
    "UMask": "0x02",
    "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
    "BriefDescription": "Cycles when L1D is locked",
    "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x04",
    "EventName": "IDQ.MITE_UOPS",
    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
    "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x04",
    "EventName": "IDQ.MITE_CYCLES_OK",
    "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
    "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "5",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x04",
    "EventName": "IDQ.MITE_CYCLES_ANY",
    "BriefDescription": "Cycles MITE is delivering any Uop",
    "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x08",
    "EventName": "IDQ.DSB_UOPS",
    "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
    "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x08",
    "EventName": "IDQ.DSB_CYCLES_OK",
    "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
    "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "5",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x08",
    "EventName": "IDQ.DSB_CYCLES_ANY",
    "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
    "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x30",
    "EventName": "IDQ.MS_SWITCHES",
    "BriefDescription": "Number of switches from DSB or MITE to the MS",
    "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "1",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x30",
    "EventName": "IDQ.MS_UOPS",
    "BriefDescription": "Uops delivered to IDQ while MS is busy",
    "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x79",
    "UMask": "0x30",
    "EventName": "IDQ.MS_CYCLES_ANY",
    "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
    "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x80",
    "UMask": "0x04",
    "EventName": "ICACHE_16B.IFDATA_STALL",
    "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
    "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "500009",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x83",
    "UMask": "0x01",
    "EventName": "ICACHE_64B.IFTAG_HIT",
    "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
    "PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x83",
    "UMask": "0x02",
    "EventName": "ICACHE_64B.IFTAG_MISS",
    "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
    "PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x83",
    "UMask": "0x04",
    "EventName": "ICACHE_64B.IFTAG_STALL",
    "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
    "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x02",
    "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
    "PublicDescription": "Counts completed page walks (4K page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x04",
    "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
    "PublicDescription": "Counts completed page walks (2M/4M page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x0e",
    "EventName": "ITLB_MISSES.WALK_COMPLETED",
    "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
    "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x10",
    "EventName": "ITLB_MISSES.WALK_PENDING",
    "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
    "PublicDescription": "Counts the number of page walks outstanding for an outstanding code (instruction fetch) request in the PMH (Page Miss Handler) each cycle.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x10",
    "EventName": "ITLB_MISSES.WALK_ACTIVE",
    "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
    "PublicDescription": "Counts cycles when at least one PMH (Page Miss Handler) is busy with a page walk for a code (instruction fetch) request.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x85",
    "UMask": "0x20",
    "EventName": "ITLB_MISSES.STLB_HIT",
    "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
    "PublicDescription": "Counts instruction fetch requests that miss the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x87",
    "UMask": "0x01",
    "EventName": "ILD_STALL.LCP",
    "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
    "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "500009",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x9C",
    "UMask": "0x01",
    "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
    "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
    "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x9c",
    "UMask": "0x01",
    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
    "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
    "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "5",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0x9C",
    "UMask": "0x01",
    "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
    "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
    "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa1",
    "UMask": "0x01",
    "EventName": "UOPS_DISPATCHED.PORT_0",
    "BriefDescription": "Number of uops executed on port 0",
    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 0.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa1",
    "UMask": "0x02",
    "EventName": "UOPS_DISPATCHED.PORT_1",
    "BriefDescription": "Number of uops executed on port 1",
    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 1.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa1",
    "UMask": "0x04",
    "EventName": "UOPS_DISPATCHED.PORT_2_3",
    "BriefDescription": "Number of uops executed on port 2 and 3",
    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 2 and 3.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa1",
    "UMask": "0x10",
    "EventName": "UOPS_DISPATCHED.PORT_4_9",
    "BriefDescription": "Number of uops executed on port 4 and 9",
    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 5 and 9.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa1",
    "UMask": "0x20",
    "EventName": "UOPS_DISPATCHED.PORT_5",
    "BriefDescription": "Number of uops executed on port 5",
    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 5.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa1",
    "UMask": "0x40",
    "EventName": "UOPS_DISPATCHED.PORT_6",
    "BriefDescription": "Number of uops executed on port 6",
    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to port 6.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa1",
    "UMask": "0x80",
    "EventName": "UOPS_DISPATCHED.PORT_7_8",
    "BriefDescription": "Number of uops executed on port 7 and 8",
    "PublicDescription": "Counts, on the per-thread basis, cycles during which at least one uop is dispatched from the Reservation Station (RS) to ports 7 and 8.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa2",
    "UMask": "0x02",
    "EventName": "RESOURCE_STALLS.SCOREBOARD",
    "BriefDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
    "PublicDescription": "Counts cycles where the pipeline is stalled due to serializing operations.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA2",
    "UMask": "0x08",
    "EventName": "RESOURCE_STALLS.SB",
    "BriefDescription": "Cycles stalled due to no store buffers available. (not including draining form sync).",
    "PublicDescription": "Counts allocation stall cycles caused by the store buffer (SB) being full. This counts cycles that the pipeline back-end blocked uop delivery from the front-end.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x01",
    "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS",
    "BriefDescription": "Cycles while L2 cache miss demand load is outstanding.",
    "PublicDescription": "Cycles while L2 cache miss demand load is outstanding.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x04",
    "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL",
    "BriefDescription": "Total execution stalls.",
    "PublicDescription": "Total execution stalls.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "4",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x05",
    "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS",
    "BriefDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
    "PublicDescription": "Execution stalls while L2 cache miss demand load is outstanding.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "5",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x06",
    "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS",
    "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
    "PublicDescription": "Execution stalls while L3 cache miss demand load is outstanding.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "6",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x08",
    "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS",
    "BriefDescription": "Cycles while L1 cache miss demand load is outstanding.",
    "PublicDescription": "Cycles while L1 cache miss demand load is outstanding.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "8",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x0C",
    "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS",
    "BriefDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
    "PublicDescription": "Execution stalls while L1 cache miss demand load is outstanding.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "12",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x10",
    "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY",
    "BriefDescription": "Cycles while memory subsystem has an outstanding load.",
    "PublicDescription": "Cycles while memory subsystem has an outstanding load.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "16",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA3",
    "UMask": "0x14",
    "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY",
    "BriefDescription": "Execution stalls while memory subsystem has an outstanding load.",
    "PublicDescription": "Execution stalls while memory subsystem has an outstanding load.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "20",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa4",
    "UMask": "0x01",
    "EventName": "TOPDOWN.SLOTS_P",
    "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
    "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "10000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa4",
    "UMask": "0x02",
    "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
    "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
    "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's  slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "10000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa4",
    "UMask": "0x08",
    "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
    "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
    "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "10000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa6",
    "UMask": "0x02",
    "EventName": "EXE_ACTIVITY.1_PORTS_UTIL",
    "BriefDescription": "Cycles total of 1 uop is executed on all ports and Reservation Station was not empty.",
    "PublicDescription": "Counts cycles during which a total of 1 uop was executed on all ports and Reservation Station (RS) was not empty.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa6",
    "UMask": "0x04",
    "EventName": "EXE_ACTIVITY.2_PORTS_UTIL",
    "BriefDescription": "Cycles total of 2 uops are executed on all ports and Reservation Station was not empty.",
    "PublicDescription": "Counts cycles during which a total of 2 uops were executed on all ports and Reservation Station (RS) was not empty.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa6",
    "UMask": "0x08",
    "EventName": "EXE_ACTIVITY.3_PORTS_UTIL",
    "BriefDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
    "PublicDescription": "Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa6",
    "UMask": "0x10",
    "EventName": "EXE_ACTIVITY.4_PORTS_UTIL",
    "BriefDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
    "PublicDescription": "Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa6",
    "UMask": "0x21",
    "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS",
    "BriefDescription": "Cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle.",
    "PublicDescription": "Counts cycles when the memory subsystem has an outstanding load. Increments by 4 for every such cycle.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "5",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA6",
    "UMask": "0x40",
    "EventName": "EXE_ACTIVITY.BOUND_ON_STORES",
    "BriefDescription": "Cycles where the Store Buffer was full and no loads caused an execution stall.",
    "PublicDescription": "Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "2",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa6",
    "UMask": "0x80",
    "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS",
    "BriefDescription": "Cycles where no uops were executed, the Reservation Station was not empty, the Store Buffer was full and there was no outstanding load.",
    "PublicDescription": "Counts cycles during which no uops were executed on all ports and Reservation Station (RS) was not empty.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA8",
    "UMask": "0x01",
    "EventName": "LSD.UOPS",
    "BriefDescription": "Number of Uops delivered by the LSD.",
    "PublicDescription": "Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xA8",
    "UMask": "0x01",
    "EventName": "LSD.CYCLES_ACTIVE",
    "BriefDescription": "Cycles Uops delivered by the LSD, but didn't come from the decoder.",
    "PublicDescription": "Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xa8",
    "UMask": "0x01",
    "EventName": "LSD.CYCLES_OK",
    "BriefDescription": "Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
    "PublicDescription": "Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "5",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xAB",
    "UMask": "0x02",
    "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
    "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
    "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xab",
    "UMask": "0x02",
    "EventName": "DSB2MITE_SWITCHES.COUNT",
    "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
    "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "1",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb0",
    "UMask": "0x01",
    "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
    "BriefDescription": "Demand Data Read requests sent to uncore",
    "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB0",
    "UMask": "0x04",
    "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
    "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
    "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb0",
    "UMask": "0x08",
    "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
    "BriefDescription": "Demand and prefetch data reads",
    "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb0",
    "UMask": "0x10",
    "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD",
    "BriefDescription": "Demand Data Read requests who miss L3 cache",
    "PublicDescription": "Demand Data Read requests who miss L3 cache.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb0",
    "UMask": "0x80",
    "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
    "BriefDescription": "Any memory transaction that reached the SQ.",
    "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED.THREAD",
    "BriefDescription": "Counts the number of uops to be executed per-thread each cycle.",
    "PublicDescription": "Counts the number of uops to be executed per-thread each cycle.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED.STALL_CYCLES",
    "BriefDescription": "Counts number of cycles no uops were dispatched to be executed on this thread.",
    "PublicDescription": "Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED.CYCLES_GE_1",
    "BriefDescription": "Cycles where at least 1 uop was executed per-thread",
    "PublicDescription": "Cycles where at least 1 uop was executed per-thread.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED.CYCLES_GE_2",
    "BriefDescription": "Cycles where at least 2 uops were executed per-thread",
    "PublicDescription": "Cycles where at least 2 uops were executed per-thread.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "2",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED.CYCLES_GE_3",
    "BriefDescription": "Cycles where at least 3 uops were executed per-thread",
    "PublicDescription": "Cycles where at least 3 uops were executed per-thread.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "3",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb1",
    "UMask": "0x01",
    "EventName": "UOPS_EXECUTED.CYCLES_GE_4",
    "BriefDescription": "Cycles where at least 4 uops were executed per-thread",
    "PublicDescription": "Cycles where at least 4 uops were executed per-thread.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "4",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x02",
    "EventName": "UOPS_EXECUTED.CORE",
    "BriefDescription": "Number of uops executed on the core.",
    "PublicDescription": "Counts the number of uops executed from any thread.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x02",
    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1",
    "BriefDescription": "Cycles at least 1 micro-op is executed from any thread on physical core.",
    "PublicDescription": "Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb1",
    "UMask": "0x02",
    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2",
    "BriefDescription": "Cycles at least 2 micro-op is executed from any thread on physical core.",
    "PublicDescription": "Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "2",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb1",
    "UMask": "0x02",
    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3",
    "BriefDescription": "Cycles at least 3 micro-op is executed from any thread on physical core.",
    "PublicDescription": "Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "3",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xb1",
    "UMask": "0x02",
    "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4",
    "BriefDescription": "Cycles at least 4 micro-op is executed from any thread on physical core.",
    "PublicDescription": "Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "4",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xB1",
    "UMask": "0x10",
    "EventName": "UOPS_EXECUTED.X87",
    "BriefDescription": "Counts the number of x87 uops dispatched.",
    "PublicDescription": "Counts the number of x87 uops executed.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xBD",
    "UMask": "0x01",
    "EventName": "TLB_FLUSH.DTLB_THREAD",
    "BriefDescription": "DTLB flush attempts of the thread-specific entries",
    "PublicDescription": "Counts the number of DTLB flush attempts of the thread-specific entries.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xbd",
    "UMask": "0x20",
    "EventName": "TLB_FLUSH.STLB_ANY",
    "BriefDescription": "STLB flush attempts",
    "PublicDescription": "Counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, etc.).",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc0",
    "UMask": "0x00",
    "EventName": "INST_RETIRED.ANY_P",
    "BriefDescription": "Number of instructions retired. General Counter - architectural event",
    "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC1",
    "UMask": "0x01",
    "EventName": "ASSISTS.PAGE_A_D",
    "BriefDescription": "Page access/dirty assists.",
    "PublicDescription": "Counts page access/dirty assists.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc1",
    "UMask": "0x02",
    "EventName": "ASSISTS.FP",
    "BriefDescription": "Counts all microcode FP assists.",
    "PublicDescription": "Counts all microcode Floating Point assists.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc1",
    "UMask": "0x07",
    "EventName": "ASSISTS.ANY",
    "BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
    "PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc2",
    "UMask": "0x02",
    "EventName": "UOPS_RETIRED.STALL_CYCLES",
    "BriefDescription": "Cycles without actually retired uops.",
    "PublicDescription": "This event counts cycles without actually retired uops.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc2",
    "UMask": "0x02",
    "EventName": "UOPS_RETIRED.TOTAL_CYCLES",
    "BriefDescription": "Cycles with less than 10 actually retired uops.",
    "PublicDescription": "Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "10",
    "Invert": "1",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc2",
    "UMask": "0x02",
    "EventName": "UOPS_RETIRED.SLOTS",
    "BriefDescription": "Retirement slots used.",
    "PublicDescription": "Counts the retirement slots used each cycle.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC3",
    "UMask": "0x01",
    "EventName": "MACHINE_CLEARS.COUNT",
    "BriefDescription": "Number of machine clears (nukes) of any type.",
    "PublicDescription": "Counts the number of machine clears (nukes) of any type.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "1",
    "Invert": "0",
    "EdgeDetect": "1",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc3",
    "UMask": "0x02",
    "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
    "BriefDescription": "Number of machine clears due to memory ordering conflicts.",
    "PublicDescription": "Counts the number of Machine Clears detected dye to memory ordering. Memory Ordering Machine Clears may apply when a memory read may not conform to the memory ordering rules of the x86 architecture",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xC3",
    "UMask": "0x04",
    "EventName": "MACHINE_CLEARS.SMC",
    "BriefDescription": "Self-modifying code (SMC) detected.",
    "PublicDescription": "Counts self-modifying code (SMC) detected, which causes a machine clear.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc4",
    "UMask": "0x00",
    "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
    "BriefDescription": "All branch instructions retired.",
    "PublicDescription": "Counts all branch instructions retired.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "400009",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc4",
    "UMask": "0x01",
    "EventName": "BR_INST_RETIRED.COND_TAKEN",
    "BriefDescription": "Taken conditional branch instructions retired.",
    "PublicDescription": "Counts taken conditional branch instructions retired.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "400009",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc4",
    "UMask": "0x02",
    "EventName": "BR_INST_RETIRED.NEAR_CALL",
    "BriefDescription": "Direct and indirect near call instructions retired.",
    "PublicDescription": "Counts both direct and indirect near call instructions retired.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc4",
    "UMask": "0x08",
    "EventName": "BR_INST_RETIRED.NEAR_RETURN",
    "BriefDescription": "Return instructions retired.",
    "PublicDescription": "Counts return instructions retired.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc4",
    "UMask": "0x10",
    "EventName": "BR_INST_RETIRED.COND_NTAKEN",
    "BriefDescription": "Not taken branch instructions retired.",
    "PublicDescription": "Counts not taken branch instructions retired.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "400009",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc4",
    "UMask": "0x11",
    "EventName": "BR_INST_RETIRED.COND",
    "BriefDescription": "Conditional branch instructions retired.",
    "PublicDescription": "Counts conditional branch instructions retired.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "400009",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc4",
    "UMask": "0x20",
    "EventName": "BR_INST_RETIRED.NEAR_TAKEN",
    "BriefDescription": "Taken branch instructions retired.",
    "PublicDescription": "Counts taken branch instructions retired.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "400009",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc4",
    "UMask": "0x40",
    "EventName": "BR_INST_RETIRED.FAR_BRANCH",
    "BriefDescription": "Far branch instructions retired.",
    "PublicDescription": "Counts far branch instructions retired.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc4",
    "UMask": "0x80",
    "EventName": "BR_INST_RETIRED.INDIRECT",
    "BriefDescription": "All indirect branch instructions retired (excluding RETs. TSX aborts are considered indirect branch).",
    "PublicDescription": "Counts all indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc5",
    "UMask": "0x00",
    "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
    "BriefDescription": "All mispredicted branch instructions retired.",
    "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "50021",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc5",
    "UMask": "0x01",
    "EventName": "BR_MISP_RETIRED.COND_TAKEN",
    "BriefDescription": "number of branch instructions retired that were mispredicted and taken. Non PEBS",
    "PublicDescription": "Counts taken conditional mispredicted branch instructions retired.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "50021",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc5",
    "UMask": "0x02",
    "EventName": "BR_MISP_RETIRED.INDIRECT_CALL",
    "BriefDescription": "Mispredicted indirect CALL instructions retired.",
    "PublicDescription": "Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "50021",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc5",
    "UMask": "0x10",
    "EventName": "BR_MISP_RETIRED.COND_NTAKEN",
    "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.",
    "PublicDescription": "Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "50021",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc5",
    "UMask": "0x11",
    "EventName": "BR_MISP_RETIRED.COND",
    "BriefDescription": "Mispredicted conditional branch instructions retired.",
    "PublicDescription": "Counts mispredicted conditional branch instructions retired.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "50021",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc5",
    "UMask": "0x20",
    "EventName": "BR_MISP_RETIRED.NEAR_TAKEN",
    "BriefDescription": "Number of near branch instructions retired that were mispredicted and taken.",
    "PublicDescription": "Counts number of near branch instructions retired that were mispredicted and taken.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "50021",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc5",
    "UMask": "0x80",
    "EventName": "BR_MISP_RETIRED.INDIRECT",
    "BriefDescription": "All miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
    "PublicDescription": "Counts all miss-predicted indirect branch instructions retired (excluding RETs. TSX aborts is considered indirect branch).",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "50021",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.DSB_MISS",
    "BriefDescription": "Retired Instructions who experienced DSB miss.",
    "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x11",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.L1I_MISS",
    "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
    "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x12",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.L2_MISS",
    "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
    "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x13",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.ITLB_MISS",
    "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
    "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x14",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.STLB_MISS",
    "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
    "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x15",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
    "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x500206",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
    "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x500406",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
    "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x500806",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
    "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x501006",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
    "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x502006",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
    "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x504006",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
    "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x508006",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
    "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x510006",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
    "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x520006",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
    "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
    "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x100206",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc6",
    "UMask": "0x01",
    "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
    "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
    "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F7",
    "MSRValue": "0x500106",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc7",
    "UMask": "0x01",
    "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
    "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "PublicDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc7",
    "UMask": "0x02",
    "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
    "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "PublicDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc7",
    "UMask": "0x04",
    "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
    "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc7",
    "UMask": "0x08",
    "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
    "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc7",
    "UMask": "0x10",
    "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
    "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "PublicDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc7",
    "UMask": "0x20",
    "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
    "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "PublicDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc7",
    "UMask": "0x40",
    "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE",
    "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "PublicDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc7",
    "UMask": "0x80",
    "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE",
    "BriefDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "PublicDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 16 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x01",
    "EventName": "RTM_RETIRED.START",
    "BriefDescription": "Number of times an RTM execution started.",
    "PublicDescription": "Counts the number of times we entered an RTM region. Does not count nested transactions.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x02",
    "EventName": "RTM_RETIRED.COMMIT",
    "BriefDescription": "Number of times an RTM execution successfully committed",
    "PublicDescription": "Counts the number of times RTM commit succeeded.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x04",
    "EventName": "RTM_RETIRED.ABORTED",
    "BriefDescription": "Number of times an RTM execution aborted.",
    "PublicDescription": "Counts the number of times RTM abort was triggered.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x08",
    "EventName": "RTM_RETIRED.ABORTED_MEM",
    "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
    "PublicDescription": "Counts the number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x20",
    "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY",
    "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
    "PublicDescription": "Counts the number of times an RTM execution aborted due to HLE-unfriendly instructions.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x40",
    "EventName": "RTM_RETIRED.ABORTED_MEMTYPE",
    "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
    "PublicDescription": "Counts the number of times an RTM execution aborted due to incompatible memory type.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xc9",
    "UMask": "0x80",
    "EventName": "RTM_RETIRED.ABORTED_EVENTS",
    "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
    "PublicDescription": "Counts the number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xcc",
    "UMask": "0x20",
    "EventName": "MISC_RETIRED.LBR_INSERTS",
    "BriefDescription": "Increments whenever there is an update to the LBR array.",
    "PublicDescription": "Increments when an entry is added to the Last Branch Record (LBR) array (or removed from the array in case of RETURNs in call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and branch type selection via MSR_LBR_SELECT.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xcc",
    "UMask": "0x40",
    "EventName": "MISC_RETIRED.PAUSE_INST",
    "BriefDescription": "Number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
    "PublicDescription": "Counts number of retired PAUSE instructions. This event is not supported on first SKL and KBL products.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "0",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xcd",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.",
    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 4 cycles.  Reported latency may be longer than just the memory latency.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x4",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xcd",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.",
    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 8 cycles.  Reported latency may be longer than just the memory latency.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "50021",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x8",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xcd",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.",
    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 16 cycles.  Reported latency may be longer than just the memory latency.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "20011",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x10",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xcd",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.",
    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 32 cycles.  Reported latency may be longer than just the memory latency.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x20",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xcd",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.",
    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 64 cycles.  Reported latency may be longer than just the memory latency.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2003",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x40",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xcd",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.",
    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 128 cycles.  Reported latency may be longer than just the memory latency.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "1009",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x80",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xcd",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.",
    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 256 cycles.  Reported latency may be longer than just the memory latency.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "503",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x100",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xcd",
    "UMask": "0x01",
    "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
    "BriefDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.",
    "PublicDescription": "Counts randomly selected loads when the latency from first dispatch to completion is greater than 512 cycles.  Reported latency may be longer than just the memory latency.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "101",
    "MSRIndex": "0x3F6",
    "MSRValue": "0x200",
    "CollectPEBSRecord": "2",
    "TakenAlone": "1",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "2",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd0",
    "UMask": "0x11",
    "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
    "BriefDescription": "Retired load instructions that miss the STLB.",
    "PublicDescription": "Counts retired load instructions that true miss the STLB.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd0",
    "UMask": "0x12",
    "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
    "BriefDescription": "Retired store instructions that miss the STLB.",
    "PublicDescription": "Counts retired store instructions that true miss the STLB.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "1",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd0",
    "UMask": "0x21",
    "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
    "BriefDescription": "Retired load instructions with locked access.",
    "PublicDescription": "Counts retired load instructions with locked access.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd0",
    "UMask": "0x41",
    "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
    "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
    "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd0",
    "UMask": "0x42",
    "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
    "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
    "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "1",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd0",
    "UMask": "0x81",
    "EventName": "MEM_INST_RETIRED.ALL_LOADS",
    "BriefDescription": "All retired load instructions.",
    "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions for loads.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd0",
    "UMask": "0x82",
    "EventName": "MEM_INST_RETIRED.ALL_STORES",
    "BriefDescription": "All retired store instructions.",
    "PublicDescription": "Counts all retired store instructions. This event account for SW prefetch instructions and PREFETCHW instruction for stores.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "1",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd1",
    "UMask": "0x01",
    "EventName": "MEM_LOAD_RETIRED.L1_HIT",
    "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
    "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "1000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd1",
    "UMask": "0x02",
    "EventName": "MEM_LOAD_RETIRED.L2_HIT",
    "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
    "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd1",
    "UMask": "0x04",
    "EventName": "MEM_LOAD_RETIRED.L3_HIT",
    "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
    "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100021",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd1",
    "UMask": "0x08",
    "EventName": "MEM_LOAD_RETIRED.L1_MISS",
    "BriefDescription": "Retired load instructions missed L1 cache as data sources",
    "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd1",
    "UMask": "0x10",
    "EventName": "MEM_LOAD_RETIRED.L2_MISS",
    "BriefDescription": "Retired load instructions missed L2 cache as data sources",
    "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100021",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd1",
    "UMask": "0x20",
    "EventName": "MEM_LOAD_RETIRED.L3_MISS",
    "BriefDescription": "Retired load instructions missed L3 cache as data sources",
    "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "50021",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd1",
    "UMask": "0x40",
    "EventName": "MEM_LOAD_RETIRED.FB_HIT",
    "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
    "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100007",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd2",
    "UMask": "0x01",
    "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
    "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
    "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "20011",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd2",
    "UMask": "0x02",
    "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
    "BriefDescription": "TBD",
    "PublicDescription": "TBD",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "20011",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd2",
    "UMask": "0x04",
    "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
    "BriefDescription": "TBD",
    "PublicDescription": "TBD",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "20011",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xd2",
    "UMask": "0x08",
    "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
    "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
    "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "1",
    "Data_LA": "1",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xE6",
    "UMask": "0x01",
    "EventName": "BACLEARS.ANY",
    "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
    "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xec",
    "UMask": "0x02",
    "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED",
    "BriefDescription": "Cycle counts are evenly distributed between active threads in the Core.",
    "PublicDescription": "This event distributes cycle counts between active hyperthreads, i.e., those in C0.  A hyperthread becomes inactive when it executes the HLT or MWAIT instructions.  If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
    "Counter": "0,1,2,3,4,5,6,7",
    "PEBScounters": "0,1,2,3,4,5,6,7",
    "SampleAfterValue": "2000003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xF0",
    "UMask": "0x40",
    "EventName": "L2_TRANS.L2_WB",
    "BriefDescription": "L2 writebacks that access L2 cache",
    "PublicDescription": "Counts L2 writebacks that access L2 cache.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xf1",
    "UMask": "0x1f",
    "EventName": "L2_LINES_IN.ALL",
    "BriefDescription": "L2 cache lines filling L2",
    "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xf2",
    "UMask": "0x01",
    "EventName": "L2_LINES_OUT.SILENT",
    "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
    "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xf2",
    "UMask": "0x02",
    "EventName": "L2_LINES_OUT.NON_SILENT",
    "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
    "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "200003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  },
  {
    "EventCode": "0xf4",
    "UMask": "0x04",
    "EventName": "SQ_MISC.SQ_FULL",
    "BriefDescription": "Cycles the superQ cannot take any more entries.",
    "PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.",
    "Counter": "0,1,2,3",
    "PEBScounters": "0,1,2,3",
    "SampleAfterValue": "100003",
    "MSRIndex": "0x00",
    "MSRValue": "0x00",
    "CollectPEBSRecord": "2",
    "TakenAlone": "0",
    "CounterMask": "0",
    "Invert": "0",
    "EdgeDetect": "0",
    "PEBS": "0",
    "Data_LA": "0",
    "L1_Hit_Indication": "0",
    "Errata": "0",
    "Offcore": "0"
  }
]