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/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,geni-se.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
23 - qcom,geni-se-qup
24 - qcom,geni-se-i2c-master-hub
30 clock-names:
38 "#address-cells":
41 "#size-cells":
[all …]
/linux/drivers/clk/imx/
H A Dclk-imx35.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
33 unsigned char arm, ahb, sel; member
37 { .arm = 1, .ahb = 4, .sel = 0},
38 { .arm = 1, .ahb = 3, .sel = 1},
39 { .arm = 2, .ahb = 2, .sel = 0},
40 { .arm = 0, .ahb = 0, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
43 { .arm = 4, .ahb = 1, .sel = 0},
[all …]
H A Dclk-imx25.c1 // SPDX-License-Identifier: GPL-2.0-or-later
47 static const char *per_sel_clks[] = { "ahb", "upll", };
48 static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
54 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, enumerator
87 clk[ahb] = imx_clk_divider("ahb", "cpu", ccm(CCM_CCTL), 28, 2); in __mx25_clocks_init()
89 clk[ipg] = imx_clk_fixed_factor("ipg", "ahb", 1, 2); in __mx25_clocks_init()
141 clk[ata_ahb] = imx_clk_gate("ata_ahb", "ahb", ccm(CCM_CGCR0), 16); in __mx25_clocks_init()
143 clk[csi_ahb] = imx_clk_gate("csi_ahb", "ahb", ccm(CCM_CGCR0), 18); in __mx25_clocks_init()
144 clk[emi_ahb] = imx_clk_gate("emi_ahb", "ahb", ccm(CCM_CGCR0), 19); in __mx25_clocks_init()
145 clk[esai_ahb] = imx_clk_gate("esai_ahb", "ahb", ccm(CCM_CGCR0), 20); in __mx25_clocks_init()
[all …]
H A Dclk-imx31.c1 // SPDX-License-Identifier: GPL-2.0-or-later
39 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, enumerator
63 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); in _mx31_clocks_init()
64 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); in _mx31_clocks_init()
65 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); in _mx31_clocks_init()
82 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14); in _mx31_clocks_init()
100 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18); in _mx31_clocks_init()
111 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8); in _mx31_clocks_init()
112 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10); in _mx31_clocks_init()
130 for_each_compatible_node(osc_np, NULL, "fixed-clock") { in mx31_clocks_init_dt()
[all …]
H A Dclk-imx6ul.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6ul-clock.h>
9 #include <linux/clk-provider.h>
13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
65 "dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
138 clk_hw_data->num = IMX6UL_CLK_END; in imx6ul_clocks_init()
139 hws = clk_hw_data->hws; in imx6ul_clocks_init()
150 np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop"); in imx6ul_clocks_init()
180 clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk); in imx6ul_clocks_init()
181 clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk); in imx6ul_clocks_init()
[all …]
/linux/drivers/soc/versatile/
H A Dsoc-integrator.c1 // SPDX-License-Identifier: GPL-2.0-only
21 { .compatible = "arm,core-module-integrator", },
29 return "ASB little-endian"; in integrator_arch_str()
31 return "AHB little-endian"; in integrator_arch_str()
33 return "AHB-Lite system bus, bi-endian"; in integrator_arch_str()
35 return "AHB"; in integrator_arch_str()
37 return "AHB system bus, ASB processor bus"; in integrator_arch_str()
70 return sprintf(buf, "%s\n", integrator_arch_str(integrator_coreid)); in arch_show()
78 return sprintf(buf, "%s\n", integrator_fpga_str(integrator_coreid)); in fpga_show()
113 return -ENODEV; in integrator_soc_init()
[all …]
/linux/drivers/clk/microchip/
H A Dclk-mpfs.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/microchip,mpfs-clock.h>
120 void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; in mpfs_clk_msspll_recalc_rate()
121 void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; in mpfs_clk_msspll_recalc_rate()
159 msspll_hw->base = data->msspll_base; in mpfs_clk_register_mssplls()
160 ret = devm_clk_hw_register(dev, &msspll_hw->hw); in mpfs_clk_register_mssplls()
165 data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; in mpfs_clk_register_mssplls()
207 msspll_out_hw->output.reg = data->msspll_base + msspll_out_hw->reg_offset; in mpfs_clk_register_msspll_outs()
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/linux/drivers/pci/controller/
H A Dpci-ixp4xx.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on the IXP4xx arch/arm/mach-ixp4xx/common-pci.c driver
9 * Copyright (C) 2003 Greg Ungerer <gerg@linux-m68k.org>
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
15 * - Test IO-space access
16 * - DMA support
113 * operates in big-endian or little-endian mode. That means that
114 * readl() and writel() that always use little-endian access
116 * when used in big-endian mode. The accesses to the individual
117 * PCI devices on the other hand, are always little-endian and
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H A Dpci-rcar-gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * pci-rcar-gen2: internal PCI bus support
26 /* AHB-PCI Bridge PCI communication registers */
108 struct rcar_pci *priv = bus->sysdata; in rcar_pci_cfg_base()
114 /* Only one EHCI/OHCI device built-in */ in rcar_pci_cfg_base()
126 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG); in rcar_pci_cfg_base()
127 return priv->reg + (slot >> 1) * 0x100 + where; in rcar_pci_cfg_base()
136 struct device *dev = priv->dev; in rcar_pci_err_irq()
137 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG); in rcar_pci_err_irq()
142 /* clear the error(s) */ in rcar_pci_err_irq()
[all …]
/linux/Documentation/devicetree/bindings/crypto/
H A Dfsl-imx-sahara.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/fsl-imx-sahara.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steffen Trumtrar <s.trumtrar@pengutronix.de>
15 - fsl,imx27-sahara
16 - fsl,imx53-sahara
23 - description: SAHARA Interrupt for Host 0
24 - description: SAHARA Interrupt for Host 1
29 - description: Sahara IPG clock
[all …]
/linux/drivers/media/platform/qcom/camss/
H A Dcamss.c1 // SPDX-License-Identifier: GPL-2.0
5 * Qualcomm MSM Camera Subsystem - Core
8 * Copyright (C) 2015-2018 Linaro Ltd.
12 #include <linux/media-bus-format.h>
24 #include <media/media-device.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-device.h>
27 #include <media/v4l2-mc.h>
28 #include <media/v4l2-fwnode.h>
41 .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" },
[all …]
/linux/drivers/usb/host/
H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
31 * This Software, including technical data, may be subject to U.S. export
32 * control laws, including the U.S. Export Administration Act and its associated
102 * Core AHB Configuration Register (GAHBCFG)
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
106 * configuration parameters. The AHB is the processor interface to the O2P USB
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
[all …]
/linux/Documentation/devicetree/bindings/bus/
H A Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
19 that is, MSI clock and AHB clock, need to be enabled so that peripherals
30 So, the controller's registers cannot be accessed by SCFW user. Hence,
32 user's point of view.
35 - $ref: simple-pm-bus.yaml#
[all …]
/linux/arch/mips/ath25/
H A Dar2315_regs.h11 * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
81 #define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
82 #define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
92 /* AHB master arbitration control */
97 #define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
106 #define AR2315_CONFIG_AHB 0x00000001 /* EC-AHB bridge endian */
108 #define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
128 /* Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0). */
163 #define AR2315_ISR_AHB 0x00000008 /* AHB error */
172 #define AR2315_GISR_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
[all …]
H A Dar5312.c9 * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
65 pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n", in ar5312_ahb_err_handler()
68 machine_restart("AHB error"); /* Catastrophic failure */ in ar5312_ahb_err_handler()
96 ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq)); in ar5312_misc_irq_unmask()
102 ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0); in ar5312_misc_irq_mask()
107 .name = "ar5312-misc",
152 if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error", in ar5312_arch_init_irq()
154 pr_err("Failed to register ar5312-ahb-error interrupt\n"); in ar5312_arch_init_irq()
168 .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
173 .name = "physmap-flash",
[all …]
/linux/Documentation/devicetree/bindings/ata/
H A Dimx-sata.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/imx-sata.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawn.guo@linaro.org>
19 - fsl,imx53-ahci
20 - fsl,imx6q-ahci
21 - fsl,imx6qp-ahci
22 - fsl,imx8qm-ahci
33 - description: sata clock
[all …]
/linux/Documentation/devicetree/bindings/display/imx/
H A Dfsl,imx-lcdc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/imx/fsl,imx-lcdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
11 - Pengutronix Kernel Team <kernel@pengutronix.de>
16 - enum:
17 - fsl,imx1-fb
18 - fsl,imx21-fb
19 - items:
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
[all …]
/linux/Documentation/ABI/testing/
H A Ddebugfs-driver-dcc6 hardware if it's ready to receive user configurations.
27 What: /sys/kernel/debug/dcc/.../[list-number]/config
35 write, read-write, and loop type. The lists need to
45 echo R <addr> <n> <bus> >/sys/kernel/debug/dcc/../[list-number]/config
58 The bus type, which can be either 'apb' or 'ahb'.
59 The default is 'ahb' if leaved out.
65 echo W <addr> <n> <bus type> > /sys/kernel/debug/dcc/../[list-number]/config
76 The bus type, which can be either 'apb' or 'ahb'.
78 iii) Read-write instruction
82 echo RW <addr> <n> <mask> > /sys/kernel/debug/dcc/../[list-number]/config
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsun6i-a31.dtsi4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/clock/sun6i-a31-ccu.h>
49 #include <dt-bindings/clock/sun6i-rtc.h>
50 #include <dt-bindings/reset/sun6i-a31-ccu.h>
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
[all …]
H A Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&intc>;
16 osc24M: clk-24M {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <24000000>;
[all …]
/linux/drivers/clk/sprd/
H A Dsc9860-clk.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/sprd,sc9860-clk.h>
25 static CLK_FIXED_FACTOR(fac_4m, "fac-4m", "ext-26m",
27 static CLK_FIXED_FACTOR(fac_2m, "fac-2m", "ext-26m",
29 static CLK_FIXED_FACTOR(fac_1m, "fac-1m", "ext-26m",
31 static CLK_FIXED_FACTOR(fac_250k, "fac-250k", "ext-26m",
33 static CLK_FIXED_FACTOR(fac_rpll0_26m, "rpll0-26m", "ext-26m",
35 static CLK_FIXED_FACTOR(fac_rpll1_26m, "rpll1-26m", "ext-26m",
37 static CLK_FIXED_FACTOR(fac_rco_25m, "rco-25m", "ext-rc0-100m",
[all …]
/linux/Documentation/devicetree/bindings/misc/
H A Daspeed-p2a-ctrl.txt2 Device tree bindings for Aspeed AST2400/AST2500 PCI-to-AHB Bridge Control Driver
6 In this case, the host has access to a 64KiB window into all of the BMC's
14 - compatible: must be one of:
15 - "aspeed,ast2400-p2a-ctrl"
16 - "aspeed,ast2500-p2a-ctrl"
21 - reg: A hint for the memory regions associated with the P2A controller
22 - memory-region: A phandle to a reserved_memory region to be used for the PCI
23 to AHB mapping
25 The p2a-control node should be the child of a syscon node with the required
28 - compatible : Should be one of the following:
[all …]
/linux/drivers/spi/
H A Dspi-nxp-fspi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright 2019-2020 NXP
14 * FlexSPI controller is driven by the LUT(Look-up Table) registers
15 * LUT registers are a look-up-table for sequences of instructions.
19 * LUTs are being created at run-time based on the commands passed
20 * from the spi-mem framework, thus using single LUT index.
24 * Memory mapped read access by AHB Bus.
26 * Based on SPI MEM interface and spi-fsl-qspi.c driver.
58 #include <linux/spi/spi-mem.h>
300 #define LUT_PAD(x) (fls(x) - 1)
[all …]
/linux/drivers/clk/sunxi/
H A Dclk-sunxi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
14 #include <linux/reset-controller.h>
19 #include "clk-factors.h"
27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
38 div = req->rate / 6000000; in sun4i_get_pll1_factors()
39 req->rate = 6000000 * div; in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
45 if (req->rate >= 768000000 || req->rate == 42000000 || in sun4i_get_pll1_factors()
46 req->rate == 54000000) in sun4i_get_pll1_factors()
[all …]

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