1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/imx6ul-clock.h>
9 #include <linux/clk-provider.h>
13 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
65 				   "dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
138 	clk_hw_data->num = IMX6UL_CLK_END;  in imx6ul_clocks_init()
139 	hws = clk_hw_data->hws;  in imx6ul_clocks_init()
150 	np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop");  in imx6ul_clocks_init()
180 	clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk);  in imx6ul_clocks_init()
181 	clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk);  in imx6ul_clocks_init()
182 	clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk);  in imx6ul_clocks_init()
183 	clk_set_parent(hws[IMX6UL_PLL4_BYPASS]->clk, hws[IMX6UL_CLK_PLL4]->clk);  in imx6ul_clocks_init()
184 	clk_set_parent(hws[IMX6UL_PLL5_BYPASS]->clk, hws[IMX6UL_CLK_PLL5]->clk);  in imx6ul_clocks_init()
185 	clk_set_parent(hws[IMX6UL_PLL6_BYPASS]->clk, hws[IMX6UL_CLK_PLL6]->clk);  in imx6ul_clocks_init()
186 	clk_set_parent(hws[IMX6UL_PLL7_BYPASS]->clk, hws[IMX6UL_CLK_PLL7]->clk);  in imx6ul_clocks_init()
197 	 * Bit 20 is the reserved and read-only bit, we do this only for:  in imx6ul_clocks_init()
198 	 * - Do nothing for usbphy clk_enable/disable  in imx6ul_clocks_init()
199 	 * - Keep refcount when do usbphy clk_enable/disable, in that case,  in imx6ul_clocks_init()
200 	 * the clk framework many need to enable/disable usbphy's parent  in imx6ul_clocks_init()
306 	hws[IMX6UL_CLK_IPG]		= imx_clk_hw_divider("ipg",	   "ahb",		base + 0x14, 8,	 2);  in imx6ul_clocks_init()
345 …hws[IMX6UL_CLK_AHB]		= imx_clk_hw_busy_divider("ahb",	    "periph",	base +  0x14, 10, 3,  base + 0…  in imx6ul_clocks_init()
348 …hws[IMX6UL_CLK_AIPSTZ1]	= imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICA…  in imx6ul_clocks_init()
349 …hws[IMX6UL_CLK_AIPSTZ2]	= imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICA…  in imx6ul_clocks_init()
351 …hws[IMX6UL_CLK_ASRC_IPG]	= imx_clk_hw_gate2_shared("asrc_ipg",	"ahb",	base + 0x68,	6, &share_count…  in imx6ul_clocks_init()
352 …hws[IMX6UL_CLK_ASRC_MEM]	= imx_clk_hw_gate2_shared("asrc_mem",	"ahb",	base + 0x68,	6, &share_count…  in imx6ul_clocks_init()
354 		hws[IMX6UL_CLK_CAAM_MEM]	= imx_clk_hw_gate2("caam_mem",	"ahb",		base + 0x68,	8);  in imx6ul_clocks_init()
355 		hws[IMX6UL_CLK_CAAM_ACLK]	= imx_clk_hw_gate2("caam_aclk",	"ahb",		base + 0x68,	10);  in imx6ul_clocks_init()
358 		hws[IMX6ULL_CLK_DCP_CLK]	= imx_clk_hw_gate2("dcp",		"ahb",		base + 0x68,	10);  in imx6ul_clocks_init()
360 		hws[IMX6UL_CLK_ENET_AHB]	= imx_clk_hw_gate2("enet_ahb",	"ahb",		base + 0x68,	12);  in imx6ul_clocks_init()
371 		hws[IMX6UL_CLK_AIPSTZ3]	= imx_clk_hw_gate2("aips_tz3",	"ahb",		 base + 0x80,	18);  in imx6ul_clocks_init()
395 …hws[IMX6ULL_CLK_ESAI_IPG]	= imx_clk_hw_gate2_shared("esai_ipg",	"ahb",		base + 0x70,	0, &share_cou…  in imx6ul_clocks_init()
396 …hws[IMX6ULL_CLK_ESAI_MEM]	= imx_clk_hw_gate2_shared("esai_mem",	"ahb",		base + 0x70,	0, &share_cou…  in imx6ul_clocks_init()
418 		hws[IMX6UL_CLK_ENET_AHB]	= imx_clk_hw_gate2("enet_ahb",	"ahb",		base + 0x74,	4);  in imx6ul_clocks_init()
446 	hws[IMX6UL_CLK_ROM]		= imx_clk_hw_gate2_flags("rom",	"ahb",		base + 0x7c,	0,	CLK_IS_CRITICAL);  in imx6ul_clocks_init()
447 	hws[IMX6UL_CLK_SDMA]		= imx_clk_hw_gate2("sdma",		"ahb",		base + 0x7c,	6);  in imx6ul_clocks_init()
491 	hws[IMX6UL_CLK_ENET1_REF_SEL] = imx_clk_gpr_mux("enet1_ref_sel", "fsl,imx6ul-iomuxc-gpr",  in imx6ul_clocks_init()
496 	hws[IMX6UL_CLK_ENET2_REF_SEL] = imx_clk_gpr_mux("enet2_ref_sel", "fsl,imx6ul-iomuxc-gpr",  in imx6ul_clocks_init()
505 	 * Lower the AHB clock rate before changing the parent clock source,  in imx6ul_clocks_init()
506 	 * as AHB clock rate can NOT be higher than 133MHz, but its parent  in imx6ul_clocks_init()
508 	 * AXI clock rate, so we need to lower AHB rate first to make sure at  in imx6ul_clocks_init()
509 	 * any time, AHB rate is <= 133MHz.  in imx6ul_clocks_init()
511 	clk_set_rate(hws[IMX6UL_CLK_AHB]->clk, 99000000);  in imx6ul_clocks_init()
514 	clk_set_parent(hws[IMX6UL_CLK_PERIPH_CLK2_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk);  in imx6ul_clocks_init()
515 	clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_CLK2]->clk);  in imx6ul_clocks_init()
516 	clk_set_parent(hws[IMX6UL_CLK_PERIPH_PRE]->clk, hws[IMX6UL_CLK_PLL2_BUS]->clk);  in imx6ul_clocks_init()
517 	clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_PRE]->clk);  in imx6ul_clocks_init()
519 	/* Make sure AHB rate is 132MHz  */  in imx6ul_clocks_init()
520 	clk_set_rate(hws[IMX6UL_CLK_AHB]->clk, 132000000);  in imx6ul_clocks_init()
523 	clk_set_parent(hws[IMX6UL_CLK_PERCLK_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk);  in imx6ul_clocks_init()
525 	clk_set_rate(hws[IMX6UL_CLK_ENET_REF]->clk, 50000000);  in imx6ul_clocks_init()
526 	clk_set_rate(hws[IMX6UL_CLK_ENET2_REF]->clk, 50000000);  in imx6ul_clocks_init()
527 	clk_set_rate(hws[IMX6UL_CLK_CSI]->clk, 24000000);  in imx6ul_clocks_init()
530 		clk_prepare_enable(hws[IMX6UL_CLK_AIPSTZ3]->clk);  in imx6ul_clocks_init()
533 		clk_prepare_enable(hws[IMX6UL_CLK_USBPHY1_GATE]->clk);  in imx6ul_clocks_init()
534 		clk_prepare_enable(hws[IMX6UL_CLK_USBPHY2_GATE]->clk);  in imx6ul_clocks_init()
537 	clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_80M]->clk);  in imx6ul_clocks_init()
539 		clk_set_parent(hws[IMX6UL_CLK_SIM_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_USB_OTG]->clk);  in imx6ul_clocks_init()
541 		clk_set_parent(hws[IMX6ULL_CLK_EPDC_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_PFD2]->clk);  in imx6ul_clocks_init()
543 	clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk);  in imx6ul_clocks_init()
545 	clk_set_parent(hws[IMX6UL_CLK_ENET1_REF_SEL]->clk, hws[IMX6UL_CLK_ENET1_REF_125M]->clk);  in imx6ul_clocks_init()
546 	clk_set_parent(hws[IMX6UL_CLK_ENET2_REF_SEL]->clk, hws[IMX6UL_CLK_ENET2_REF_125M]->clk);  in imx6ul_clocks_init()
551 CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init);