1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved.
7 #include <linux/clk-provider.h>
11 #include <dt-bindings/clock/microchip,mpfs-clock.h>
120 	void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset;  in mpfs_clk_msspll_recalc_rate()
121 	void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR;  in mpfs_clk_msspll_recalc_rate()
159 		msspll_hw->base = data->msspll_base;  in mpfs_clk_register_mssplls()
160 		ret = devm_clk_hw_register(dev, &msspll_hw->hw);  in mpfs_clk_register_mssplls()
165 		data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw;  in mpfs_clk_register_mssplls()
207 		msspll_out_hw->output.reg = data->msspll_base + msspll_out_hw->reg_offset;  in mpfs_clk_register_msspll_outs()
208 		ret = devm_clk_hw_register(dev, &msspll_out_hw->output.hw);  in mpfs_clk_register_msspll_outs()
211 					     msspll_out_hw->id);  in mpfs_clk_register_msspll_outs()
213 		data->hw_data.hws[msspll_out_hw->id] = &msspll_out_hw->output.hw;  in mpfs_clk_register_msspll_outs()
267 		cfg_hw->cfg.reg = data->base + cfg_hw->reg_offset;  in mpfs_clk_register_cfgs()
268 		ret = devm_clk_hw_register(dev, &cfg_hw->cfg.hw);  in mpfs_clk_register_cfgs()
271 					     cfg_hw->id);  in mpfs_clk_register_cfgs()
273 		id = cfg_hw->id;  in mpfs_clk_register_cfgs()
274 		data->hw_data.hws[id] = &cfg_hw->cfg.hw;  in mpfs_clk_register_cfgs()
281  * peripheral clocks - devices connected to axi or ahb buses.
296  * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m mode interrupt
298  * - CLK_MMUART0: reserved by the hss
299  * - CLK_DDRC: provides clock to the ddr subsystem
300  * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc will stop
301  *   if the AHB interface clock is disabled
302  * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric InterConnect)
305  * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena TeraFire.
309 	CLK_PERIPH(CLK_ENVM, "clk_periph_envm", PARENT_CLK(AHB), 0, CLK_IS_CRITICAL),
310 	CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", PARENT_CLK(AHB), 1, 0),
311 	CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", PARENT_CLK(AHB), 2, 0),
312 	CLK_PERIPH(CLK_MMC, "clk_periph_mmc", PARENT_CLK(AHB), 3, 0),
314 	CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", PARENT_CLK(AHB), 5, CLK_IS_CRITICAL),
315 	CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", PARENT_CLK(AHB), 6, 0),
316 	CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", PARENT_CLK(AHB), 7, 0),
317 	CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", PARENT_CLK(AHB), 8, 0),
318 	CLK_PERIPH(CLK_MMUART4, "clk_periph_mmuart4", PARENT_CLK(AHB), 9, 0),
319 	CLK_PERIPH(CLK_SPI0, "clk_periph_spi0", PARENT_CLK(AHB), 10, 0),
320 	CLK_PERIPH(CLK_SPI1, "clk_periph_spi1", PARENT_CLK(AHB), 11, 0),
321 	CLK_PERIPH(CLK_I2C0, "clk_periph_i2c0", PARENT_CLK(AHB), 12, 0),
322 	CLK_PERIPH(CLK_I2C1, "clk_periph_i2c1", PARENT_CLK(AHB), 13, 0),
323 	CLK_PERIPH(CLK_CAN0, "clk_periph_can0", PARENT_CLK(AHB), 14, 0),
324 	CLK_PERIPH(CLK_CAN1, "clk_periph_can1", PARENT_CLK(AHB), 15, 0),
325 	CLK_PERIPH(CLK_USB, "clk_periph_usb", PARENT_CLK(AHB), 16, 0),
326 	CLK_PERIPH(CLK_RTC, "clk_periph_rtc", PARENT_CLK(AHB), 18, CLK_IS_CRITICAL),
327 	CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", PARENT_CLK(AHB), 19, 0),
328 	CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", PARENT_CLK(AHB), 20, 0),
329 	CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", PARENT_CLK(AHB), 21, 0),
330 	CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", PARENT_CLK(AHB), 22, 0),
331 	CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", PARENT_CLK(AHB), 23, CLK_IS_CRITICAL),
337 	CLK_PERIPH(CLK_CFM, "clk_periph_cfm", PARENT_CLK(AHB), 29, 0),
349 		periph_hw->periph.reg = data->base + REG_SUBBLK_CLOCK_CR;  in mpfs_clk_register_periphs()
350 		ret = devm_clk_hw_register(dev, &periph_hw->periph.hw);  in mpfs_clk_register_periphs()
353 					     periph_hw->id);  in mpfs_clk_register_periphs()
356 		data->hw_data.hws[id] = &periph_hw->periph.hw;  in mpfs_clk_register_periphs()
364 	struct device *dev = &pdev->dev;  in mpfs_clk_probe()
375 		return -ENOMEM;  in mpfs_clk_probe()
377 	clk_data->base = devm_platform_ioremap_resource(pdev, 0);  in mpfs_clk_probe()
378 	if (IS_ERR(clk_data->base))  in mpfs_clk_probe()
379 		return PTR_ERR(clk_data->base);  in mpfs_clk_probe()
381 	clk_data->msspll_base = devm_platform_ioremap_resource(pdev, 1);  in mpfs_clk_probe()
382 	if (IS_ERR(clk_data->msspll_base))  in mpfs_clk_probe()
383 		return PTR_ERR(clk_data->msspll_base);  in mpfs_clk_probe()
385 	clk_data->hw_data.num = num_clks;  in mpfs_clk_probe()
386 	clk_data->dev = dev;  in mpfs_clk_probe()
409 	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clk_data->hw_data);  in mpfs_clk_probe()
413 	return mpfs_reset_controller_register(dev, clk_data->base + REG_SUBBLK_RESET_CR);  in mpfs_clk_probe()
417 	{ .compatible = "microchip,mpfs-clkcfg", },
425 		.name = "microchip-mpfs-clkcfg",