/freebsd/sys/contrib/device-tree/Bindings/serial/ |
H A D | st,stm32-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 - Erwan Le Ray <erwan.leray@foss.st.com> 15 - st,stm32-uart 16 - st,stm32f7-uart 17 - st,stm32h7-uart 34 st,hw-flow-ctrl: 38 rx-tx-swap: true [all …]
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H A D | serial.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Rob Herring <robh@kernel.org> 11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org> 19 where N is the port number (non-negative decimal integer) as printed on the 28 cts-gpios: 34 dcd-gpios: 40 dsr-gpios: 46 dtr-gpios: [all …]
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/freebsd/sys/contrib/device-tree/Bindings/usb/ |
H A D | dwc3.txt | 3 DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties 7 - compatible: must be "snps,dwc3" 8 - reg : Address and length of the register set for the device 9 - interrupts: Interrupts used by the dwc3 controller. 10 - clock-names: list of clock names. Ideally should be "ref", 12 - clocks: list of phandle and clock specifier pairs corresponding to 13 entries in the clock-names property. 16 clocks are optional if the parent node (i.e. glue-layer) is compatible to 18 "cavium,octeon-7130-usb-uctl" 20 "samsung,exynos5250-dwusb3" [all …]
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H A D | snps,dwc3.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Felipe Balbi <balbi@kernel.org> 14 be presented as a standalone DT node with an optional vendor-specific 18 - $ref: usb-drd.yaml# 19 - if: 25 - dr_mode 29 $ref: usb-xhci.yaml# 35 - const: snps,dwc3 [all …]
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/freebsd/sys/gnu/dev/bwn/phy_n/ |
H A D | if_bwn_phy_n_regs.h | 22 Boston, MA 02110-1301, USA. 32 /* N-PHY registers. */ 36 #define BWN_NPHY_BBCFG_RSTRX 0x8000 /* Reset RX */ 41 #define BWN_NPHY_4WI_ADDR BWN_PHY_N(0x00B) /* Four-wire bus address */ 42 #define BWN_NPHY_4WI_DATAHI BWN_PHY_N(0x00C) /* Four-wire bus data high */ 43 #define BWN_NPHY_4WI_DATALO BWN_PHY_N(0x00D) /* Four-wire bus data low */ 44 #define BWN_NPHY_BIST_STAT0 BWN_PHY_N(0x00E) /* Built-in self test status 0 */ 45 #define BWN_NPHY_BIST_STAT1 BWN_PHY_N(0x00F) /* Built-in self test status 1 */ 80 #define BWN_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */ 93 #define BWN_NPHY_C1_CLIPWBTHRES BWN_PHY_N(0x027) /* Core 1 clip wideband threshold */ [all …]
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/freebsd/sys/contrib/dev/iwlwifi/fw/api/ |
H A D | power.h | 1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 3 * Copyright (C) 2012-2014, 2018-2024 Intel Corporation 4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 13 * enum iwl_ltr_config_flags - mask [all...] |
/freebsd/sys/dev/igc/ |
H A D | igc_regs.h | 1 /*- 4 * SPDX-License-Identifier: BSD-3-Clause 11 #define IGC_CTRL 0x00000 /* Device Control - RW */ 12 #define IGC_STATUS 0x00008 /* Device Status - RO */ 13 #define IGC_EECD 0x00010 /* EEPROM/Flash Control - RW */ 15 #define IGC_EERD 0x12014 /* EEprom mode read - RW */ 16 #define IGC_EEWR 0x12018 /* EEprom mode write - RW */ 17 #define IGC_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 18 #define IGC_MDIC 0x00020 /* MDI Control - RW */ 19 #define IGC_MDICNFG 0x00E04 /* MDI Config - RW */ [all …]
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H A D | igc_defines.h | 1 /*- 4 * SPDX-License-Identifier: BSD-3-Clause 72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 98 #define IGC_RXD_ERR_RXE 0x80 /* Rx Data Error */ 127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 153 #define IGC_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ 160 #define IGC_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 161 #define IGC_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ [all …]
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/freebsd/sys/contrib/device-tree/Bindings/sound/ |
H A D | qcom,wcd93xx-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/qcom,wcd93xx-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> 13 reset-gpios: 17 vdd-buck-supply: 20 vdd-rxtx-supply: 21 description: A reference to the 1.8V rx supply 23 vdd-io-supply: [all …]
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H A D | davinci-mcasp-audio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/davinci-mcasp-audio.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Jayesh Choudhary <j-choudhary@ti.com> 15 - ti,dm646x-mcasp-audio 16 - ti,da830-mcasp-audio 17 - ti,am33xx-mcasp-audio 18 - ti,dra7-mcasp-audio 19 - ti,omap4-mcasp-audio [all …]
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/freebsd/sys/net/ |
H A D | paravirt.h | 31 Support for virtio-like communication between host (H) and guest (G) NICs. 37 csb->csb_on enables the mode. If disabled, the device acts a regular one. 39 Notifications for tx and rx are exchanged without vm exits 74 and one with a threshold (using guest_txkick_at). They are mutually 79 THRESHOLD: G sets guest_txkick_at to the TDH value for which it 85 RX: start from idle 92 RX: active state 98 RX: H runs out of buffers 100 and one with a threshold (using host_xxkick_at). They are mutually 105 THRESHOLD: H sets host_rxkick_at to the RDT value for which it wants [all …]
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/freebsd/crypto/openssl/doc/designs/quic-design/ |
H A D | quic-fc.md | 5 --------------------------------- 8 transmission of stream data could be prevented by connection-level flow control, 9 by stream-level flow control, or both. Flow control uses a credit-based model in 14 It is important to note that both connection and stream-level flow control 32 Connection-level flow control is controlled by the `MAX_DATA` frame; 33 stream-level flow control is controlled by the `MAX_STREAM_DATA` frame. 38 our connection-level credit, and a conformant QUIC implementation can choose to 43 Note that it follows from the above that the CRYPTO-frame stream is not subject 54 | |<-- credit| -->| | 55 | <-|- threshold -|----->| | [all …]
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/freebsd/sys/dev/e1000/ |
H A D | e1000_regs.h | 2 SPDX-License-Identifier: BSD-3-Clause 4 Copyright (c) 2001-2020, Intel Corporation 38 #define E1000_CTRL 0x00000 /* Device Control - RW */ 39 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 40 #define E1000_STATUS 0x00008 /* Device Status - RO */ 41 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 42 #define E1000_EERD 0x00014 /* EEPROM Read - RW */ 43 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 44 #define E1000_FLA 0x0001C /* Flash Access - RW */ 45 #define E1000_MDIC 0x00020 /* MDI Control - RW */ [all …]
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H A D | e1000_defines.h | 2 SPDX-License-Identifier: BSD-3-Clause 4 Copyright (c) 2001-2020, Intel Corporation 94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 132 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 198 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min thresh size */ 205 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 206 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ [all …]
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/freebsd/sys/contrib/device-tree/Bindings/phy/ |
H A D | phy-stm32-usbphyc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 22 |_ PHY port#2 ----| |________________ 27 - Amelie Delaunay <amelie.delaunay@foss.st.com> 31 const: st,stm32mp1-usbphyc 42 "#address-cells": 45 "#size-cells": 48 vdda1v1-supply: [all …]
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/freebsd/sys/dev/neta/ |
H A D | if_mvnetareg.h | 46 /* XXX: Currently multi-queue can be used on the Tx side only */ 53 #if MVNETA_TX_QNUM_MAX & (MVNETA_TX_QNUM_MAX - 1) != 0 56 #if MVNETA_RX_QNUM_MAX & (MVNETA_RX_QNUM_MAX - 1) != 0 62 #define MVNETA_TX_QUEUE_ALL ((1<<MVNETA_TX_QNUM_MAX)-1) 63 #define MVNETA_RX_QUEUE_ALL ((1<<MVNETA_RX_QNUM_MAX)-1) 99 /* Rx DMA Hardware Parser Registers */ 117 /* Rx DMA Miscellaneous Registers */ 118 #define MVNETA_PMFS 0x247c /* Port Rx Minimal Frame Size */ 119 #define MVNETA_PDFC 0x2484 /* Port Rx Discard Frame Counter */ 123 /* Rx DMA Networking Controller Miscellaneous Registers */ [all …]
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/freebsd/sys/dev/cas/ |
H A D | if_casreg.h | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 30 * from: FreeBSD: if_gemreg.h 174987 2007-12-30 01:32:03Z marius 73 #define CAS_CAW_RX_WGHT_MASK 0x00000003 /* RX DMA factor for... */ 75 #define CAS_CAW_TX_WGHT_MASK 0x0000000c /* RX DMA factor for... */ 84 * Bits 0-9 of CAS_STATUS auto-clear when read. CAS_CLEAR_ALIAS specifies 85 * which of bits 0-9 auto-clear when reading CAS_STATUS_ALIAS. 91 #define CAS_INTR_RX_DONE 0x00000010 /* >=1 RX frames transferred. */ 92 #define CAS_INTR_RX_BUF_NA 0x00000020 /* RX buffer not available */ 93 #define CAS_INTR_RX_TAG_ERR 0x00000040 /* RX FIFO tag corrupted. */ [all …]
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/freebsd/sys/contrib/alpine-hal/ |
H A D | al_hal_serdes_interface.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html 53 /* *INDENT-OFF* */ 57 /* *INDENT-ON* */ 101 * Transmits the untimed, partial equalized RX signal out the transmit 114 * Loops back the TX driver IO signal to the RX IO pins 129 /** Loops TX data (to PMA) to RX path (instead of PMA data) */ 178 * Tx de-emphasis parameters 183 AL_SERDES_TX_DEEMP_C_MINUS, /*< c(-1) */ 196 * Transmit Amplitude control signal. Used to define the full-scale 198 * 000 - Not Supported [all …]
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H A D | al_hal_udma_regs_s2m.h | 1 /*- 10 found at http://www.gnu.org/licenses/gpl-2.0.html 86 * 00 - No pending tasks 100 * 0 - Log is enable 101 * 1 - Log is masked. 190 * [0x8] Counting the net length of the data buffers [64-bit] 195 * [0xc] Counting the net length of the data buffers [64-bit] 246 /* [0x28] Rx Descriptor Ring Base Pointer [31:4] */ 248 /* [0x2c] Rx Descriptor Ring Base Pointer [63:32] */ 251 * [0x30] Rx Descriptor Ring Length[23:2] [all …]
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/freebsd/sys/dev/ath/ath_hal/ar5416/ |
H A D | ar5416reg.h | 1 /*- 2 * SPDX-License-Identifier: ISC 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 27 #define AR_MIRT 0x0020 /* interrupt rate threshold */ 28 #define AR_TIMT 0x0028 /* Tx Interrupt mitigation threshold */ 29 #define AR_RIMT 0x002C /* Rx Interrupt mitigation threshold */ 34 #define AR_WA 0x4004 /* PCIE work-arounds */ 120 /* RTC_DERIVED_* - only for AR9130 */ 129 #define AR5416_USEC_RX_LAT 0x1F800000 /* rx latency to start of SIGNAL (usec) */ [all …]
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/freebsd/sys/contrib/device-tree/Bindings/firmware/ |
H A D | arm,scmi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Sudeep Holla <sudeep.holla@arm.com> 26 - $ref: /schemas/firmware/nxp,imx95-scmi.yaml 34 - description: SCMI compliant firmware with mailbox transport 36 - const: arm,scmi 37 - description: SCMI compliant firmware with ARM SMC/HVC transport 39 - const: arm,scmi-smc 40 - description: SCMI compliant firmware with ARM SMC/HVC transport [all …]
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/freebsd/crypto/openssl/test/ |
H A D | quic_ackm_test.c | 2 * Copyright 2022-2025 The OpenSSL Project Authors. All Rights Reserved. 32 ++info->lost; in on_lost() 38 ++info->acked; in on_acked() 44 ++info->discarded; in on_discarded() 60 if (h->ackm != NULL) { in helper_destroy() 61 ossl_ackm_free(h->ackm); in helper_destroy() 62 h->ackm = NULL; in helper_destroy() 65 if (h->ccdata != NULL) { in helper_destroy() 66 ossl_cc_dummy_method.free(h->ccdata); in helper_destroy() 67 h->ccdata = NULL; in helper_destroy() [all …]
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/freebsd/sys/dev/usb/serial/ |
H A D | umcs.h | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 50 #define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong 52 #define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong 67 #define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */ 78 /* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */ 105 #define MCS7840_DEV_REG_RX_SAMPLING12 0x30 /* RX sampling for ports 1 & 107 #define MCS7840_DEV_REG_RX_SAMPLING34 0x31 /* RX sampling for ports 3 & 109 #define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port 112 #define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port [all …]
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/freebsd/sys/dev/ath/ath_hal/ar5210/ |
H A D | ar5210reg.h | 1 /*- 2 * SPDX-License-Identifier: ISC 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2004 Atheros Communications, Inc. 24 * Processor for IEEE 802.11a 5-GHz Wireless LANs. 37 #define AR_RXDP 0x000c /* RX queue descriptor ptr register */ 45 #define AR_RXCFG 0x0034 /* RX configuration register */ 48 #define AR_RXNOFRM 0x0048 /* RX no frame timeout register */ 50 #define AR_RPGTO 0x0050 /* RX frame gap timeout register */ 51 #define AR_RFCNT 0x0054 /* RX frame count limit register */ [all …]
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/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
H A D | ar9300reg.h | 32 /* MAC Control Register - only write values of 1 have effect */ 37 #define AR_CR_SWI 0x00000040 // One-shot software interrupt 44 #define AR_CFG_SWRD 0x00000004 // byteswap rx descriptor words 45 #define AR_CFG_SWRB 0x00000008 // byteswap rx data buffer words 47 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 // AP/adhoc indication (0-AP 1-Adhoc) 51 …PCI_MASTER_REQ_Q_THRESH 0x00060000 // Mask of PCI core master request queue full threshold 52 …I_MASTER_REQ_Q_THRESH_S 17 // Shift for PCI core master request queue full threshold 55 /* Rx DMA Data Buffer Pointer Threshold - High and Low Priority register */ 62 /* Tx DMA Descriptor Pointer Threshold register */ 65 /* Mac Interrupt rate threshold register */ [all …]
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