Lines Matching +full:rx +full:- +full:threshold
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
22 /* QE I-RAM */
24 __be32 iadd; /* I-RAM Address Register */
25 __be32 idata; /* I-RAM Data Register */
27 __be32 iready; /* I-RAM Ready Register */
63 __be32 cetscr; /* QE time-stamp timer control register */
64 __be32 cetsr1; /* QE time-stamp register 1 */
65 __be32 cetsr2; /* QE time-stamp register 2 */
171 u8 sirarc1; /* SI1 RAM counter Rx TDMA */
172 u8 sirbrc1; /* SI1 RAM counter Rx TDMB */
173 u8 sircrc1; /* SI1 RAM counter Rx TDMC */
174 u8 sirdrc1; /* SI1 RAM counter Rx TDMD */
191 u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */
192 u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */
193 u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */
194 u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */
204 u8 rx[0x400]; member
240 __be16 upsmr; /* UCCx protocol-specific mode register */
258 __be32 upsmr; /* UCCx protocol-specific mode register */
270 __be16 urfet; /* UCC receive FIFO emergency threshold */
272 threshold */
276 __be16 utfet; /* UCC transmit FIFO emergency threshold */
278 __be16 utftt; /* UCC transmit FIFO transmit threshold */
305 __be32 upstpa; /* UTOPIA/POS STPA threshold */
355 __be32 sdtr1; /* SDMA system bus threshold register */
356 __be32 sdtr2; /* SDMA secondary bus threshold register */
420 u8 res4[0x100-0xf8];
424 struct qe_iram iram; /* I-RAM */
449 struct dbg dbg; /* 0x104080 - 0x1040FF
451 struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF
454 u8 res14[0x300]; /* 0x104300 - 0x1045FF */
455 u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */
456 u8 res16[0x8000]; /* 0x108000 - 0x110000 */
457 u8 muram[0xC000]; /* 0x110000 - 0x11C000
458 Multi-user RAM */
459 u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
460 u8 res18[0xC0000]; /* 0x140000 - 0x200000 */