Lines Matching +full:rx +full:- +full:threshold
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
14 driver Copyright(c) 2003 - 2004 Intel Corporation.
49 /* OFDM (A) registers of a G-PHY */
51 /* Extended G-PHY registers */
55 /* Extended G-PHY Registers */
57 #define B43legacy_PHY_GTABCTL B43legacy_PHY_EXTG(0x03) /* G-PHY table control (see below) */
58 #define B43legacy_PHY_GTABOFF 0x03FF /* G-PHY table offset (see below) */
59 #define B43legacy_PHY_GTABNR 0xFC00 /* G-PHY table number (see below) */
61 #define B43legacy_PHY_GTABDATA B43legacy_PHY_EXTG(0x04) /* G-PHY table data */
104 #define B43legacy_PHY_VERSION_OFDM B43legacy_PHY_OFDM(0x00) /* Versioning register for A-PHY */
106 #define B43legacy_PHY_BBANDCFG_RXANT 0x180 /* RX Antenna selection */
109 #define B43legacy_PHY_CRSTHRES1 B43legacy_PHY_OFDM(0x06) /* CRS Threshold 1 */
114 #define B43legacy_PHY_ANTDWELL_AUTODIV1 0x0100 /* Automatic RX diversity start antenna */
128 #define B43legacy_PHY_NRSSITHRES B43legacy_PHY_OFDM(0x8A) /* NRSSI threshold */
130 #define B43legacy_PHY_ANTWRSETT_ARXDIV 0x2000 /* Automatic RX diversity enabled */
131 #define B43legacy_PHY_CLIPPWRDOWNT B43legacy_PHY_OFDM(0x93) /* Clip powerdown threshold */
144 #define B43legacy_PHY_CRSTHRES1_R1 B43legacy_PHY_OFDM(0xC0) /* CRS Threshold 1 (rev 1 only) */
145 #define B43legacy_PHY_CRSTHRES2_R1 B43legacy_PHY_OFDM(0xC1) /* CRS Threshold 2 (rev 1 only) */
166 (((phy)->rev > 1) || ((phy)->gmode))