Lines Matching +full:rx +full:- +full:threshold
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
64 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
125 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */
131 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */
132 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */
133 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */
134 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */
136 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */
137 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */
138 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */
183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
238 /* 1000/H is not supported, nor spec-compliant. */
290 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
292 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
384 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */
385 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */
387 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */
395 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */
396 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */
412 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
436 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
437 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
439 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */
445 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */
446 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */
453 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */
454 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */
458 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
459 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */
460 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */
504 /* Loop limit on how long we wait for auto-negotiation to complete */
528 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
544 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */
545 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */
551 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */
587 /* NVM Addressing bits based on type (0-small, 1-large) */
647 /* NVM Commands - SPI */
651 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
679 /* PCI/PCI-X/PCI-EX Config space */
683 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
720 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
730 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */
760 * 15-5: page
761 * 4-0: register offset
784 /* Page 193 - Port Control Registers */
790 /* Page 194 - KMRN Registers */