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/linux/Documentation/devicetree/bindings/net/
H A Dnvidia,tegra234-mgbe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nvidia,tegra234-mgbe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra234 MGBE Multi-Gigabit Ethernet Controller
10 - Thierry Reding <treding@nvidia.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 const: nvidia,tegra234-mgbe
20 reg-names:
22 - const: hypervisor
[all …]
/linux/include/uapi/linux/
H A Dmdio.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
4 * Copyright 2006-2009 Solarflare Communications Inc.
25 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
59 /* Media-dependent registers. */
60 #define MDIO_PMA_10GBT_SWAPPOL 130 /* 10GBASE-T pair swap & polarity */
61 #define MDIO_PMA_10GBT_TXPWR 131 /* 10GBASE-T TX power control */
62 #define MDIO_PMA_10GBT_SNR 133 /* 10GBASE-T SNR margin, lane A.
63 * Lanes B-D are numbered 134-136. */
64 #define MDIO_PMA_10GBR_FSRT_CSR 147 /* 10GBASE-R fast retrain status and control */
65 #define MDIO_PMA_10GBR_FECABLE 170 /* 10GBASE-R FEC ability */
[all …]
/linux/drivers/thunderbolt/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 Apple hardware or on PCs with Intel Falcon Ridge or newer.
16 To compile this driver a module, choose M here. The module will be
56 dongle that has TX/RX lines crossed, or by simply connecting a
60 To compile this driver a module, choose M here. The module will be
/linux/drivers/net/phy/
H A Dmicrochip_t1.c1 // SPDX-License-Identifier: GPL-2.0
104 /* DSP 100M registers */
112 /* DSP 1000M registers */
123 /* PCS 1000M registers */
139 /* PCS 100M registers */
266 #define SQI_INLIERS_START ((SQI_SAMPLES - SQI_INLIERS_NUM) / 2)
274 /* TEST_MODE_NORMAL: Non-hybrid results to calculate cable status(open/short/ok)
307 { "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14},
308 { "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16},
310 { "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8},
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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_ethtool.c1 // SPDX-License-Identifier: GPL-2.0-only
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
45 #define STMMAC_STAT(m) \ argument
46 { #m, sizeof_field(struct stmmac_extra_stats, m), \
47 offsetof(struct stmmac_priv, xstats.m)}
80 /* Tx/Rx IRQ error info */
90 /* Tx/Rx IRQ Events */
130 /* PCS */
168 /* statistics collected in queue which will be summed up for all TX or RX
169 * queues, or summed up for both TX and RX queues(napi_poll, normal_irq_n).
[all …]
/linux/drivers/net/ethernet/sun/
H A Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
42 * if rx weight == 1 and tx weight == 0, rx == 2x tx transfer credit
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
81 from RX FIFO to host mem.
82 RX completion reg updated.
86 RX Kick == RX complete */
[all …]
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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/linux/drivers/net/ethernet/intel/igb/
H A De1000_82575.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
61 * igb_write_vfta_i350 - Write value to VLAN filter table
71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350()
74 for (i = 10; i--;) in igb_write_vfta_i350()
78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350()
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575()
114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap()
[all …]
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
135 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
138 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
139 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
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/linux/drivers/net/ethernet/meta/fbnic/
H A Dfbnic_csr.h1 /* SPDX-License-Identifier: GPL-2.0 */
93 /* Rx Buffer Descriptor Format
110 (FBNIC_BD_DESC_ADDR_MASK & ~(FBNIC_BD_DESC_ADDR_MASK - 1))
124 /* Rx Completion Queue Descriptors */
137 #define FBNIC_RCD_AL_BUFF_FRAG_MASK (FBNIC_BD_FRAG_COUNT - 1)
296 /* Global QM Rx registers */
420 #define FBNIC_TCE_RAM_TCAM(m, n) \ argument
421 (0x04200 + 0x8 * (n) + (m)) /* 0x10800 + 32*n + 4*m */
474 /* Rx Buffer Registers */
591 /* Rx Parser and Classifier Registers */
[all …]
/linux/drivers/net/ethernet/chelsio/cxgb/
H A Dvsc7326_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Straight off the data sheet, VMDS-10038 Rev 2.0 and
9 * PD0011-01-14-Meigs-II 2002-12-12
69 * fn = FIFO number, 0-9
84 * bn = bucket number 0-10 (yes, 11 buckets)
114 #define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */
133 * tri-speed are only defined with the version that needs a port number.
140 /* 10GbE specific, and different from tri-speed */
144 #define REG_STICKY_RX CRA(0x1,0xa,0x06) /* RX debug register */
147 #define REG_MAX_RXHIGH CRA(0x1,0xa,0x0a) /* XGMII lane 0-3 debug */
[all …]
/linux/Documentation/networking/device_drivers/ethernet/cirrus/
H A Dcs89x0.rst1 .. SPDX-License-Identifier: GPL-2.0
33 2.1 CS8900-based Adapter Configuration
34 2.2 CS8920-based Adapter Configuration
41 4.3 Compiling the driver to support Rx DMA
46 5.2.1 Diagnostic Self-Test
66 The CS8900-based ISA Ethernet Adapters from Cirrus Logic follow
67 IEEE 802.3 standards and support half or full-duplex operation in ISA bus
69 in 16-bit ISA or EISA bus expansion slots and are available in
70 10BaseT-only or 3-media configurations (10BaseT, 10Base2, and AUI for 10Base-5
73 CS8920-based adapters are similar to the CS8900-based adapter with additional
[all …]
/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
422 /* MAC decode size is 128K - This is the size of BAR0 */
443 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
486 * E1000_RAR_ENTRIES - 1 multicast addresses.
503 /* Receive Descriptor - Extended */
511 __le32 mrq; /* Multiple Rx Queues */
529 /* Receive Descriptor - Packet Split */
537 __le32 mrq; /* Multiple Rx Queues */
553 __le16 length[3]; /* length of buffers 1-3 */
[all …]
/linux/drivers/scsi/bfa/
H A Dbfa_defs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
4 * Copyright (c) 2014- QLogic Corporation.
8 * Linux driver for QLogic BR-series Fibre Channel Host Bus Adapter.
34 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /* Lightning mezz card - old */
72 #define bfa_mfg_increment_wwn_mac(m, i) \ argument
74 u32 t = ((u32)(m)[0] << 16) | ((u32)(m)[1] << 8) | \
75 (u32)(m)[2]; \
77 (m)[0] = (t >> 16) & 0xFF; \
78 (m)[1] = (t >> 8) & 0xFF; \
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/linux/drivers/net/dsa/
H A Dmt7530.c1 // SPDX-License-Identifier: GPL-2.0-only
28 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) in pcs_to_mt753x_pcs() argument
30 return container_of(pcs, struct mt753x_pcs, pcs); in pcs_to_mt753x_pcs()
81 if (priv->bus) in mt7530_mutex_lock()
82 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
88 if (priv->bus) in mt7530_mutex_unlock()
89 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
95 struct mii_bus *bus = priv->bus; in core_write()
101 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
107 ret = bus->write(bus, MT753X_CTRL_PHY_ADDR(priv->mdiodev->addr), in core_write()
[all …]
/linux/drivers/phy/samsung/
H A Dphy-exynos5-usbdrd.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include <linux/soc/samsung/exynos-regs-pmu.h>
194 /* Exynos9 - GS101 */
234 /* PCS registers */
300 #define PHY_TUNING_ENTRY_PHY(o, m, v) { \ argument
302 .mask = (m), \
307 #define PHY_TUNING_ENTRY_PCS(o, m, v) { \ argument
309 .mask = (m), \
314 #define PHY_TUNING_ENTRY_PMA(o, m, v) { \ argument
316 .mask = (m), \
[all …]
/linux/drivers/net/dsa/realtek/
H A Drtl8365mb.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
9 * can be connected to the CPU - or another PHY - via either MII, RMII, or
15 * .-----------------------------------.
17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |
18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC |
19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC |
[all …]
/linux/drivers/net/ethernet/sfc/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
[all …]
/linux/drivers/net/ethernet/mscc/
H A Docelot.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
30 /* Caller must hold &ocelot->mact_lock */
36 /* Caller must hold &ocelot->mact_lock */
48 /* Caller must hold &ocelot->mact_lock */
90 if (mc_ports & BIT(ocelot->num_phys_ports)) in __ocelot_mact_learn()
109 mutex_lock(&ocelot->mact_lock); in ocelot_mact_learn()
111 mutex_unlock(&ocelot->mact_lock); in ocelot_mact_learn()
122 mutex_lock(&ocelot->mact_lock); in ocelot_mact_forget()
133 mutex_unlock(&ocelot->mact_lock); in ocelot_mact_forget()
145 mutex_lock(&ocelot->mact_lock); in ocelot_mact_lookup()
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/linux/Documentation/admin-guide/media/
H A Dbttv.rst1 .. SPDX-License-Identifier: GPL-2.0
8 ----------------------
12 ./scripts/config -e PCI
13 ./scripts/config -m I2C
14 ./scripts/config -m INPUT
15 ./scripts/config -m MEDIA_SUPPORT
16 ./scripts/config -e MEDIA_PCI_SUPPORT
17 ./scripts/config -e MEDIA_ANALOG_TV_SUPPORT
18 ./scripts/config -e MEDIA_DIGITAL_TV_SUPPORT
19 ./scripts/config -e MEDIA_RADIO_SUPPORT
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
H A Danx7625.c1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
50 struct device *dev = &client->dev; in i2c_access_workaround()
53 if (client == ctx->last_client) in i2c_access_workaround()
56 ctx->last_client = client; in i2c_access_workaround()
58 if (client == ctx->i2c.tcpc_client) in i2c_access_workaround()
60 else if (client == ctx->i2c.tx_p0_client) in i2c_access_workaround()
62 else if (client == ctx->i2c.tx_p1_client) in i2c_access_workaround()
64 else if (client == ctx->i2c.rx_p0_client) in i2c_access_workaround()
[all …]
/linux/drivers/net/ethernet/sfc/siena/
H A Dmcdi_pcol.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
38 /* The rest of these are firmware-defined */
46 /* Values to be written to the per-port status dword in shared
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
[all …]
/linux/
H A DMAINTAINERS5 ---------------------------------------------------
7 M: *Mail* patches to: FullName <address@domain>
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
71 M: Steffen Klassert <klassert@kernel.org>
78 M: David Dillow <dave@thedillows.org>
[all …]
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-mdio.c9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
127 #include "xgbe-common.h"
132 if (!pdata->phy_if.phy_impl.module_eeprom) in xgbe_phy_module_eeprom()
133 return -ENXIO; in xgbe_phy_module_eeprom()
135 return pdata->phy_if.phy_impl.module_eeprom(pdata, eeprom, data); in xgbe_phy_module_eeprom()
141 if (!pdata->phy_if.phy_impl.module_info) in xgbe_phy_module_info()
142 return -ENXIO; in xgbe_phy_module_info()
144 return pdata->phy_if.phy_impl.module_info(pdata, modinfo); in xgbe_phy_module_info()
199 switch (pdata->an_mode) { in xgbe_an_enable_interrupts()
[all …]
/linux/drivers/net/ethernet/intel/e1000e/
H A Dethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
28 "s0ix-enabled",
33 #define E1000_STAT(str, m) { \ argument
36 .sizeof_stat = sizeof(((struct e1000_adapter *)0)->m), \
37 .stat_offset = offsetof(struct e1000_adapter, m) }
38 #define E1000_NETDEV_STAT(str, m) { \ argument
41 .sizeof_stat = sizeof(((struct rtnl_link_stats64 *)0)->m), \
42 .stat_offset = offsetof(struct rtnl_link_stats64, m) }
115 struct e1000_hw *hw = &adapter->hw; in e1000_get_link_ksettings()
[all …]

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