Lines Matching +full:rx +full:- +full:pcs +full:- +full:m
1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
50 struct device *dev = &client->dev;
53 if (client == ctx->last_client)
56 ctx->last_client = client;
58 if (client == ctx->i2c.tcpc_client)
60 else if (client == ctx->i2c.tx_p0_client)
62 else if (client == ctx->i2c.tx_p1_client)
64 else if (client == ctx->i2c.rx_p0_client)
66 else if (client == ctx->i2c.rx_p1_client)
75 client->addr, offset);
84 struct device *dev = &client->dev;
91 client->addr, reg_addr);
101 struct device *dev = &client->dev;
108 client->addr, reg_addr);
118 struct device *dev = &client->dev;
126 client->addr, reg_addr);
136 struct device *dev = &client->dev;
143 client->addr, reg_addr);
192 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
195 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
204 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS);
209 struct device *dev = ctx->dev;
220 return -EIO;
223 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
227 return -EIO;
236 struct device *dev = ctx->dev;
244 return -EINVAL;
259 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
263 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
265 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
267 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
271 ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client,
274 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
279 return -EIO;
293 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
297 return -EIO;
310 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
312 /* Clear mipi RX en */
313 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
317 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
319 /* Set MIPI RX EN */
320 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
361 unsigned long *m,
370 return -EINVAL;
378 return -EINVAL;
394 return -EDOM;
414 return -EDOM;
417 *m = pixelclock;
420 anx7625_reduction_of_a_fraction(m, n);
429 struct device *dev = ctx->dev;
432 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
434 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
437 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
439 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8,
442 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */
443 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
447 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
449 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
469 drm_edid_get_product_id(ctx->cached_drm_edid, &id);
472 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
475 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
481 struct device *dev = ctx->dev;
482 unsigned long m, n;
487 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000,
488 &m, &n, &post_divider);
491 DRM_DEV_ERROR(dev, "cannot get property m n value.\n");
495 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n",
496 m, n, post_divider);
499 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L,
500 (ctx->dt.pixelclock.min / 1000) & 0xFF);
501 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H,
502 (ctx->dt.pixelclock.min / 1000) >> 8);
504 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
506 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client,
507 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1);
510 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min +
511 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min;
512 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
514 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
517 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
518 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF);
519 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
520 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8);
522 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
523 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min);
524 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
526 ctx->dt.hfront_porch.min >> 8);
528 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
529 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min);
530 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
531 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8);
533 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
534 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min);
535 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
536 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8);
538 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L,
539 ctx->dt.vactive.min);
540 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H,
541 ctx->dt.vactive.min >> 8);
543 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
544 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min);
546 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
547 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min);
549 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
550 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min);
551 /* M value */
552 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
553 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff);
554 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
555 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff);
556 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
557 MIPI_PLL_M_NUM_7_0, (m & 0xff));
559 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
561 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
563 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0,
568 ret |= anx7625_odfc_config(ctx, post_divider - 1);
579 struct device *dev = ctx->dev;
581 /* Swap MIPI-DSI data lane 3 P and N */
582 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP);
585 return -EIO;
589 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val);
596 struct device *dev = ctx->dev;
598 /* Swap MIPI-DSI data lane 3 P and N */
614 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
621 * P332 D-PHY Probe) default D-PHY timing
624 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
628 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18,
637 /* Toggle m, n ready */
638 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
641 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
645 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
647 /* Power on MIPI RX */
648 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
650 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
661 struct device *dev = ctx->dev;
667 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
677 /* Set MIPI RX EN */
678 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
681 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
684 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n");
693 struct device *dev = ctx->dev;
694 u16 freq = ctx->dt.pixelclock.min / 1000;
698 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
700 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
705 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
708 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
711 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
714 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
724 struct device *dev = ctx->dev;
730 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
749 /* set MIPI RX EN */
750 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
753 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
756 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n");
763 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL);
769 struct device *dev = ctx->dev;
772 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
774 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
781 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
782 FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8);
783 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
784 FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF);
790 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
799 return -EIO;
802 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
807 return -EIO;
811 return -EINVAL;
819 struct device *dev = ctx->dev;
822 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
824 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
826 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
828 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
830 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
833 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
835 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
838 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
847 struct device *dev = ctx->dev;
852 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
854 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
856 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
860 return anx7625_write_and(ctx, ctx->i2c.tx_p0_client,
868 struct device *dev = ctx->dev;
889 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
894 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
899 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
902 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client,
910 ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20);
913 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
915 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
919 return anx7625_write_or(ctx, ctx->i2c.tx_p0_client,
926 struct device *dev = ctx->dev;
929 if (!ctx->display_timing_valid) {
942 anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
944 if (ctx->pdata.is_dpi)
952 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
954 ctx->dp_en = 1;
959 struct device *dev = ctx->dev;
969 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe);
970 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f);
981 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED;
983 ctx->dp_en = 0;
990 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
992 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
1001 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1003 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1005 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1014 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1016 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1024 struct device *dev = ctx->dev;
1028 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START);
1031 return -EIO;
1046 struct device *dev = ctx->dev;
1057 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
1067 return -EIO;
1077 struct device *dev = ctx->dev;
1080 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1082 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1084 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1092 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1108 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
1117 return -EIO;
1132 struct device *dev = ctx->dev;
1135 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1137 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1139 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
1143 return -EIO;
1224 return -EINVAL;
1239 struct device *dev = ctx->dev;
1242 if (!ctx->pdata.low_power_mode) {
1247 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) {
1248 ret = regulator_enable(ctx->pdata.supplies[i].consumer);
1260 gpiod_set_value(ctx->pdata.gpio_p_on, 1);
1263 gpiod_set_value(ctx->pdata.gpio_reset, 1);
1269 for (--i; i >= 0; i--)
1270 regulator_disable(ctx->pdata.supplies[i].consumer);
1275 struct device *dev = ctx->dev;
1278 if (!ctx->pdata.low_power_mode) {
1283 gpiod_set_value(ctx->pdata.gpio_reset, 0);
1285 gpiod_set_value(ctx->pdata.gpio_p_on, 0);
1288 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies),
1289 ctx->pdata.supplies);
1299 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1308 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
1310 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
1313 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
1322 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, GPIO_CTRL_2);
1327 struct device *dev = ctx->dev;
1331 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40);
1333 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1336 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00);
1360 struct device *dev = ctx->dev;
1363 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1370 return -ENODEV;
1376 ctx->i2c.rx_p0_client,
1379 ctx->i2c.rx_p0_client,
1406 struct device *dev = platform->dev;
1411 platform->pdata.gpio_p_on =
1413 if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) {
1415 platform->pdata.gpio_p_on = NULL;
1419 platform->pdata.gpio_reset =
1421 if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) {
1423 platform->pdata.gpio_reset = NULL;
1426 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) {
1427 platform->pdata.low_power_mode = 1;
1429 desc_to_gpio(platform->pdata.gpio_p_on),
1430 desc_to_gpio(platform->pdata.gpio_reset));
1432 platform->pdata.low_power_mode = 0;
1439 ctx->hpd_status = 0;
1440 ctx->hpd_high_cnt = 0;
1446 struct device *dev = ctx->dev;
1448 if (ctx->hpd_high_cnt >= 2) {
1453 ctx->hpd_status = 1;
1454 ctx->hpd_high_cnt++;
1457 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
1460 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
1462 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
1468 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86);
1477 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS);
1484 struct device *dev = ctx->dev;
1487 if (ctx->pdata.intp_irq)
1501 anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1503 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1508 if (!ctx->pdata.panel_bridge && ctx->bridge_attached)
1509 drm_helper_hpd_irq_event(ctx->bridge.dev);
1518 struct device *dev = ctx->dev;
1531 drm_edid_free(ctx->cached_drm_edid);
1532 ctx->cached_drm_edid = NULL;
1539 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++)
1540 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client,
1542 ctx->pdata.lane0_reg_data[i]);
1544 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++)
1545 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client,
1547 ctx->pdata.lane1_reg_data[i]);
1552 struct device *dev = ctx->dev;
1572 struct device *dev = ctx->dev;
1574 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1581 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1588 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1597 return -ENOENT;
1599 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1618 mutex_lock(&ctx->lock);
1620 if (pm_runtime_suspended(ctx->dev)) {
1621 mutex_unlock(&ctx->lock);
1627 mutex_unlock(&ctx->lock);
1632 if (ctx->bridge_attached)
1633 drm_helper_hpd_irq_event(ctx->bridge.dev);
1640 queue_work(ctx->workqueue, &ctx->work);
1650 num_regs = of_property_read_variable_u8_array(dev->of_node, "analogix,lane0-swing",
1651 pdata->lane0_reg_data, 1, DP_TX_SWING_REG_CNT);
1653 pdata->dp_lane0_swing_reg_cnt = num_regs;
1655 num_regs = of_property_read_variable_u8_array(dev->of_node, "analogix,lane1-swing",
1656 pdata->lane1_reg_data, 1, DP_TX_SWING_REG_CNT);
1658 pdata->dp_lane1_swing_reg_cnt = num_regs;
1666 struct device_node *np = dev->of_node, *ep0;
1671 pdata->is_dpi = 0; /* default dsi mode */
1672 of_node_put(pdata->mipi_host_node);
1673 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0);
1674 if (!pdata->mipi_host_node) {
1676 return -ENODEV;
1683 if (of_property_read_u32(ep0, "bus-type", &bus_type))
1691 pdata->is_dpi = 1;
1693 pdata->mipi_lanes = MAX_LANES_SUPPORT;
1695 pdata->mipi_lanes = mipi_lanes;
1697 if (pdata->is_dpi)
1702 if (of_property_read_bool(np, "analogix,audio-enable"))
1703 pdata->audio_en = 1;
1711 struct device_node *np = dev->of_node;
1713 pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0);
1714 if (IS_ERR(pdata->panel_bridge)) {
1715 if (PTR_ERR(pdata->panel_bridge) == -ENODEV) {
1716 pdata->panel_bridge = NULL;
1720 return PTR_ERR(pdata->panel_bridge);
1732 bus = of_get_child_by_name(dev->of_node, "aux-bus");
1754 struct device *dev = ctx->dev;
1755 u8 request = msg->request & ~DP_AUX_I2C_MOT;
1758 mutex_lock(&ctx->aux_lock);
1760 msg->reply = 0;
1768 ret = -EINVAL;
1771 ret = anx7625_aux_trans(ctx, msg->request, msg->address,
1772 msg->size, msg->buffer);
1775 mutex_unlock(&ctx->aux_lock);
1782 struct device *dev = ctx->dev;
1786 if (ctx->cached_drm_edid)
1804 ctx->cached_drm_edid = drm_edid_alloc(edid_buf, FOUR_BLOCK_SIZE);
1808 return drm_edid_dup(ctx->cached_drm_edid);
1813 struct device *dev = ctx->dev;
1817 if (ctx->pdata.panel_bridge)
1820 return ctx->hpd_status ? connector_status_connected :
1837 if (fmt->fmt != HDMI_DSP_A && fmt->fmt != HDMI_I2S) {
1839 return -EINVAL;
1843 params->sample_rate, params->sample_width,
1844 params->cea.channels);
1846 if (fmt->fmt == HDMI_DSP_A)
1847 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1852 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1858 switch (params->sample_width) {
1873 params->sample_width);
1874 return -EINVAL;
1876 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1881 switch (params->cea.channels) {
1896 params->cea.channels);
1897 return -EINVAL;
1899 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1902 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
1905 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client,
1909 switch (params->sample_rate) {
1933 params->sample_rate);
1934 return -EINVAL;
1936 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
1939 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
1943 return -EIO;
1977 if (ctx->plugged_cb && ctx->codec_dev) {
1978 ctx->plugged_cb(ctx->codec_dev,
1989 ctx->plugged_cb = fn;
1990 ctx->codec_dev = codec_dev;
2001 if (!ctx->connector) {
2006 mutex_lock(&ctx->connector->eld_mutex);
2007 memcpy(buf, ctx->connector->eld,
2008 min(sizeof(ctx->connector->eld), len));
2009 mutex_unlock(&ctx->connector->eld_mutex);
2025 struct device *dev = ctx->dev;
2027 if (ctx->audio_pdev) {
2028 platform_device_unregister(ctx->audio_pdev);
2029 ctx->audio_pdev = NULL;
2044 ctx->audio_pdev = platform_device_register_data(dev,
2050 if (IS_ERR(ctx->audio_pdev))
2051 return PTR_ERR(ctx->audio_pdev);
2061 struct device *dev = ctx->dev;
2069 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node);
2071 return dev_err_probe(dev, -EPROBE_DEFER, "fail to find dsi host.\n");
2076 return -EINVAL;
2079 dsi->lanes = ctx->pdata.mipi_lanes;
2080 dsi->format = MIPI_DSI_FMT_RGB888;
2081 dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
2086 ctx->dsi = dsi;
2093 struct device *dev = ctx->dev;
2098 ret = devm_mipi_dsi_attach(dev, ctx->dsi);
2119 dev = ctx->dev;
2121 if (!ctx->connector) {
2126 drm_dev = ctx->connector->dev;
2127 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
2128 mutex_lock(&ctx->hdcp_wq_lock);
2130 status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0);
2133 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED;
2134 drm_hdcp_update_content_protection(ctx->connector,
2135 ctx->hdcp_cp);
2139 mutex_unlock(&ctx->hdcp_wq_lock);
2140 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
2148 struct device *dev = ctx->dev;
2152 return -EINVAL;
2154 ctx->aux.drm_dev = bridge->dev;
2155 err = drm_dp_aux_register(&ctx->aux);
2161 if (ctx->pdata.panel_bridge) {
2162 err = drm_bridge_attach(bridge->encoder,
2163 ctx->pdata.panel_bridge,
2164 &ctx->bridge, flags);
2169 ctx->bridge_attached = 1;
2178 drm_dp_aux_unregister(&ctx->aux);
2187 struct device *dev = ctx->dev;
2191 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */
2192 if (mode->clock > SUPPORT_PIXEL_CLOCK) {
2208 struct device *dev = ctx->dev;
2212 ctx->dt.pixelclock.min = mode->clock;
2213 ctx->dt.hactive.min = mode->hdisplay;
2214 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start;
2215 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay;
2216 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end;
2217 ctx->dt.vactive.min = mode->vdisplay;
2218 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start;
2219 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay;
2220 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end;
2222 ctx->display_timing_valid = 1;
2224 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min);
2226 ctx->dt.hactive.min,
2227 ctx->dt.hsync_len.min,
2228 ctx->dt.hfront_porch.min,
2229 ctx->dt.hback_porch.min);
2231 ctx->dt.vactive.min,
2232 ctx->dt.vsync_len.min,
2233 ctx->dt.vfront_porch.min,
2234 ctx->dt.vback_porch.min);
2236 mode->hdisplay,
2237 mode->hsync_start);
2239 mode->hsync_end,
2240 mode->htotal);
2242 mode->vdisplay,
2243 mode->vsync_start);
2245 mode->vsync_end,
2246 mode->vtotal);
2254 struct device *dev = ctx->dev;
2262 if (!ctx->pdata.panel_bridge)
2265 hsync = mode->hsync_end - mode->hsync_start;
2266 hfp = mode->hsync_start - mode->hdisplay;
2267 hbp = mode->htotal - mode->hsync_end;
2268 hblanking = mode->htotal - mode->hdisplay;
2272 hsync, hfp, hbp, adj->clock);
2274 adj->hsync_start, adj->hsync_end, adj->htotal);
2289 adj_hbp -= 1;
2290 adj_hblanking -= 1;
2298 adj_hsync -= 1;
2303 * This adjusting made for built-in eDP panel, for the externel
2310 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal);
2312 delta_adj = HBLANKING_MIN - hblanking;
2313 adj_clock = vref * delta_adj * adj->vtotal;
2314 adj->clock += DIV_ROUND_UP(adj_clock, 1000);
2316 delta_adj = hblanking - HBLANKING_MIN;
2317 adj_clock = vref * delta_adj * adj->vtotal;
2318 adj->clock -= DIV_ROUND_UP(adj_clock, 1000);
2325 delta_adj = HP_MIN - adj_hfp;
2332 if ((adj_hbp - delta_adj) < HP_MIN)
2334 adj_hsync -= delta_adj;
2336 adj_hbp -= delta_adj;
2338 delta_adj = HP_MIN - adj_hbp;
2345 if ((adj_hfp - delta_adj) < HP_MIN)
2347 adj_hsync -= delta_adj;
2349 adj_hfp -= delta_adj;
2354 adj_hsync, adj_hfp, adj_hbp, adj->clock);
2357 adj->hsync_start = adj->hdisplay + adj_hfp;
2358 adj->hsync_end = adj->hsync_start + adj_hsync;
2359 adj->htotal = adj->hsync_end + adj_hbp;
2361 adj->hsync_start, adj->hsync_end, adj->htotal);
2372 struct device *dev = ctx->dev;
2376 anx7625_bridge_mode_fixup(bridge, &crtc_state->mode,
2377 &crtc_state->adjusted_mode);
2386 struct device *dev = ctx->dev;
2392 connector = drm_atomic_get_new_connector_for_encoder(state->base.state,
2393 bridge->encoder);
2397 ctx->connector = connector;
2404 conn_state = drm_atomic_get_new_connector_state(state->base.state, connector);
2409 if (conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
2410 if (ctx->dp_en) {
2414 queue_delayed_work(ctx->hdcp_workqueue,
2415 &ctx->hdcp_work,
2425 struct device *dev = ctx->dev;
2429 flush_workqueue(ctx->hdcp_workqueue);
2431 if (ctx->connector &&
2432 ctx->hdcp_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
2434 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_DESIRED;
2435 drm_hdcp_update_content_protection(ctx->connector,
2436 ctx->hdcp_cp);
2440 ctx->connector = NULL;
2443 mutex_lock(&ctx->aux_lock);
2445 mutex_unlock(&ctx->aux_lock);
2456 struct device *dev = ctx->dev;
2470 struct device *dev = ctx->dev;
2495 struct device *dev = ctx->dev;
2497 ctx->i2c.tx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter,
2499 if (IS_ERR(ctx->i2c.tx_p0_client))
2500 return PTR_ERR(ctx->i2c.tx_p0_client);
2502 ctx->i2c.tx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter,
2504 if (IS_ERR(ctx->i2c.tx_p1_client))
2505 return PTR_ERR(ctx->i2c.tx_p1_client);
2507 ctx->i2c.tx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter,
2509 if (IS_ERR(ctx->i2c.tx_p2_client))
2510 return PTR_ERR(ctx->i2c.tx_p2_client);
2512 ctx->i2c.rx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter,
2514 if (IS_ERR(ctx->i2c.rx_p0_client))
2515 return PTR_ERR(ctx->i2c.rx_p0_client);
2517 ctx->i2c.rx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter,
2519 if (IS_ERR(ctx->i2c.rx_p1_client))
2520 return PTR_ERR(ctx->i2c.rx_p1_client);
2522 ctx->i2c.rx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter,
2524 if (IS_ERR(ctx->i2c.rx_p2_client))
2525 return PTR_ERR(ctx->i2c.rx_p2_client);
2527 ctx->i2c.tcpc_client = devm_i2c_new_dummy_device(dev, client->adapter,
2529 if (IS_ERR(ctx->i2c.tcpc_client))
2530 return PTR_ERR(ctx->i2c.tcpc_client);
2539 mutex_lock(&ctx->lock);
2542 if (!ctx->pdata.panel_bridge)
2546 mutex_unlock(&ctx->lock);
2555 mutex_lock(&ctx->lock);
2559 mutex_unlock(&ctx->lock);
2580 struct device *dev = aux->dev;
2583 ret = anx7625_parse_dt_panel(dev, &platform->pdata);
2589 platform->bridge.funcs = &anx7625_bridge_funcs;
2590 platform->bridge.of_node = dev->of_node;
2592 platform->bridge.ops |= DRM_BRIDGE_OP_EDID;
2593 if (!platform->pdata.panel_bridge)
2594 platform->bridge.ops |= DRM_BRIDGE_OP_HPD |
2596 platform->bridge.type = platform->pdata.panel_bridge ?
2600 drm_bridge_add(&platform->bridge);
2602 if (!platform->pdata.is_dpi) {
2605 drm_bridge_remove(&platform->bridge);
2616 struct device *dev = &client->dev;
2618 if (!i2c_check_functionality(client->adapter,
2621 return -ENODEV;
2627 return -ENOMEM;
2630 pdata = &platform->pdata;
2632 platform->dev = &client->dev;
2635 pdata->supplies[0].supply = "vdd10";
2636 pdata->supplies[1].supply = "vdd18";
2637 pdata->supplies[2].supply = "vdd33";
2638 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies),
2639 pdata->supplies);
2646 mutex_init(&platform->lock);
2647 mutex_init(&platform->hdcp_wq_lock);
2648 mutex_init(&platform->aux_lock);
2650 INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func);
2651 platform->hdcp_workqueue = create_workqueue("hdcp workqueue");
2652 if (!platform->hdcp_workqueue) {
2654 ret = -ENOMEM;
2658 platform->pdata.intp_irq = client->irq;
2659 if (platform->pdata.intp_irq) {
2660 INIT_WORK(&platform->work, anx7625_work_func);
2661 platform->workqueue = alloc_workqueue("anx7625_work",
2663 if (!platform->workqueue) {
2665 ret = -ENOMEM;
2669 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq,
2673 "anx7625-intp", platform);
2680 platform->aux.name = "anx7625-aux";
2681 platform->aux.dev = dev;
2682 platform->aux.transfer = anx7625_aux_transfer;
2683 platform->aux.wait_hpd_asserted = anx7625_wait_hpd_asserted;
2684 drm_dp_aux_init(&platform->aux);
2688 if (ret != -EPROBE_DEFER)
2693 if (!platform->pdata.is_dpi) {
2705 ret = -ENOMEM;
2723 ret = devm_of_dp_aux_populate_bus(&platform->aux, anx7625_link_bridge);
2725 if (ret != -ENODEV) {
2730 ret = anx7625_link_bridge(&platform->aux);
2735 if (!platform->pdata.low_power_mode) {
2742 if (platform->pdata.intp_irq)
2743 queue_work(platform->workqueue, &platform->work);
2745 if (platform->pdata.audio_en)
2753 if (platform->workqueue)
2754 destroy_workqueue(platform->workqueue);
2757 if (platform->hdcp_workqueue)
2758 destroy_workqueue(platform->hdcp_workqueue);
2767 drm_bridge_remove(&platform->bridge);
2769 if (platform->pdata.intp_irq)
2770 destroy_workqueue(platform->workqueue);
2772 if (platform->hdcp_workqueue) {
2773 cancel_delayed_work(&platform->hdcp_work);
2774 flush_workqueue(platform->hdcp_workqueue);
2775 destroy_workqueue(platform->hdcp_workqueue);
2778 if (!platform->pdata.low_power_mode)
2779 pm_runtime_put_sync_suspend(&client->dev);
2781 if (platform->pdata.audio_en)