Home
last modified time | relevance | path

Searched full:reg_bit (Results 1 – 25 of 29) sorted by relevance

12

/linux/drivers/gpu/drm/xe/regs/
H A Dxe_gt_regs.h57 #define MCR_MULTICAST REG_BIT(31)
72 #define LE_SCF_MASK REG_BIT(14)
78 #define LE_RSC_MASK REG_BIT(7)
80 #define LE_AOM_MASK REG_BIT(6)
93 #define EN_CMP_1WCOH REG_BIT(15)
94 #define CG_DIS_CNTLBUS REG_BIT(6)
102 #define AUX_INV REG_BIT(0)
105 #define DIS_PEND_GPA_LINK REG_BIT(13)
108 #define STLB_SINGLE_BANK_MODE REG_BIT(11)
115 #define EN_CMP_1WCOH_GW REG_BIT(14)
[all …]
H A Dxe_engine_regs.h64 #define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12)
65 #define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7)
66 #define IDLE_MSG_DISABLE REG_BIT(0)
96 #define ENABLE_SEMAPHORE_POLL_BIT REG_BIT(13)
101 #define SELECTIVE_READ_ADDRESSING REG_BIT(30)
116 #define GHWSP_CSB_REPORT_DIS REG_BIT(15)
117 #define PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS REG_BIT(14)
118 #define CS_PRIORITY_MEM_READ REG_BIT(7)
121 #define INSTRUCTION_STATE_CACHE_INVALIDATE REG_BIT(6)
124 #define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14)
[all …]
H A Dxe_mchbar_regs.h42 #define PWR_LIM_EN REG_BIT(15)
/linux/drivers/gpu/drm/i915/display/
H A Dintel_psr_regs.h14 #define EXITLINE_ENABLE REG_BIT(31)
28 #define EDP_PSR_ENABLE REG_BIT(31)
29 #define BDW_PSR_SINGLE_FRAME REG_BIT(30)
30 #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK REG_BIT(29) /* SW can't modify */
31 #define EDP_PSR_LINK_STANDBY REG_BIT(27)
41 #define EDP_PSR_SKIP_AUX_EXIT REG_BIT(12)
42 #define EDP_PSR_TP_MASK REG_BIT(11)
45 #define EDP_PSR_CRC_ENABLE REG_BIT(10) /* BDW+ */
75 #define TGL_PSR_ERROR REG_BIT(2)
76 #define TGL_PSR_POST_EXIT REG_BIT(1)
[all …]
H A Dintel_dvo_regs.h15 #define DVO_ENABLE REG_BIT(31)
16 #define DVO_PIPE_SEL_MASK REG_BIT(30)
22 #define DVO_INTERRUPT_SELECT REG_BIT(27)
23 #define DVO_DEDICATED_INT_ENABLE REG_BIT(26)
25 #define DVO_USE_VGA_SYNC REG_BIT(15)
26 #define DVO_DATA_ORDER_MASK REG_BIT(14)
29 #define DVO_VSYNC_DISABLE REG_BIT(11)
30 #define DVO_HSYNC_DISABLE REG_BIT(10)
31 #define DVO_VSYNC_TRISTATE REG_BIT(9)
32 #define DVO_HSYNC_TRISTATE REG_BIT(8)
[all …]
H A Dintel_dp_aux_regs.h46 #define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31)
47 #define DP_AUX_CH_CTL_DONE REG_BIT(30)
48 #define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29)
49 #define DP_AUX_CH_CTL_TIME_OUT_ERROR REG_BIT(28)
55 #define DP_AUX_CH_CTL_RECEIVE_ERROR REG_BIT(25)
60 #define XELPDP_DP_AUX_CH_CTL_POWER_REQUEST REG_BIT(19) /* mtl+ */
61 #define XELPDP_DP_AUX_CH_CTL_POWER_STATUS REG_BIT(18) /* mtl+ */
62 #define DP_AUX_CH_CTL_AUX_AKSV_SELECT REG_BIT(15)
63 #define DP_AUX_CH_CTL_MANCHESTER_TEST REG_BIT(14) /* pre-hsw */
64 #define DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL REG_BIT(14) /* skl+ */
[all …]
H A Dvlv_dpio_phy_regs.h41 #define DPIO_ENABLE_CALIBRATION REG_BIT(11)
48 #define DPIO_REFSEL_OVERRIDE REG_BIT(27)
75 #define DPIO_PCS_TX_LANE2_RESET REG_BIT(16)
76 #define DPIO_PCS_TX_LANE1_RESET REG_BIT(7)
77 #define DPIO_LEFT_TXFIFO_RST_MASTER2 REG_BIT(4)
78 #define DPIO_RIGHT_TXFIFO_RST_MASTER2 REG_BIT(3)
83 #define CHV_PCS_REQ_SOFTRESET_EN REG_BIT(23)
84 #define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN REG_BIT(22)
85 #define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN REG_BIT(21)
90 #define DPIO_PCS_CLK_SOFT_RESET REG_BIT(5)
[all …]
H A Dbxt_dpio_phy_regs.h37 #define PORT_PLL_ENABLE REG_BIT(31)
38 #define PORT_PLL_LOCK REG_BIT(30)
39 #define PORT_PLL_REF_SEL REG_BIT(27)
40 #define PORT_PLL_POWER_ENABLE REG_BIT(26)
41 #define PORT_PLL_POWER_STATE REG_BIT(25)
58 #define PORT_PLL_RECALIBRATE REG_BIT(14)
59 #define PORT_PLL_10BIT_CLK_ENABLE REG_BIT(13)
77 #define PORT_PLL_M2_FRAC_ENABLE REG_BIT(16)
92 #define PORT_PLL_DCO_AMP_OVR_EN_H REG_BIT(27)
104 #define PHY_POWER_GOOD REG_BIT(16)
[all …]
H A Dintel_sprite_regs.h13 #define DVS_ENABLE REG_BIT(31)
14 #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
15 #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
21 #define DVS_PIPE_CSC_ENABLE REG_BIT(24)
22 #define DVS_SOURCE_KEY REG_BIT(22)
23 #define DVS_RGB_ORDER_XBGR REG_BIT(20)
24 #define DVS_YUV_FORMAT_BT709 REG_BIT(18)
30 #define DVS_ROTATE_180 REG_BIT(15)
31 #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
32 #define DVS_TILED REG_BIT(10)
[all …]
H A Di9xx_plane_regs.h16 #define DISP_ENABLE REG_BIT(31)
17 #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
32 #define DISP_STEREO_ENABLE REG_BIT(25)
33 #define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
36 #define DISP_SRC_KEY_ENABLE REG_BIT(22)
37 #define DISP_LINE_DOUBLE REG_BIT(20)
38 #define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
39 #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
40 #define DISP_ROTATE_180 REG_BIT(15) /* i965+ */
41 #define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) /* pre-g4x plane B */
[all …]
H A Dskl_universal_plane_regs.h38 #define PLANE_CTL_ENABLE REG_BIT(31)
41 #define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */
42 #define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
67 #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */
71 #define PLANE_CTL_ORDER_RGBX REG_BIT(20)
72 #define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19)
73 #define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18)
79 #define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15)
80 #define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14)
81 #define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */
[all …]
H A Dintel_snps_phy_regs.h29 #define SNPS_PHY_MPLLB_FORCE_EN REG_BIT(31)
30 #define SNPS_PHY_MPLLB_DIV_CLK_EN REG_BIT(30)
31 #define SNPS_PHY_MPLLB_DIV5_CLK_EN REG_BIT(29)
35 #define SNPS_PHY_MPLLB_PMIX_EN REG_BIT(10)
36 #define SNPS_PHY_MPLLB_DP2_MODE REG_BIT(9)
37 #define SNPS_PHY_MPLLB_WORD_DIV2_EN REG_BIT(8)
39 #define SNPS_PHY_MPLLB_SHIM_DIV32_CLK_SEL REG_BIT(0)
42 #define SNPS_PHY_MPLLB_FRACN_EN REG_BIT(31)
43 #define SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN REG_BIT(30)
51 #define SNPS_PHY_MPLLB_SSC_EN REG_BIT(31)
[all …]
H A Dintel_audio_regs.h12 #define G4X_ELD_VALID REG_BIT(14)
15 #define G4X_ELD_ACK REG_BIT(4)
28 #define IBX_ELD_ACK REG_BIT(4)
30 #define IBX_CP_READY(port) REG_BIT(((port) - 1) * 4 + 1)
31 #define IBX_ELD_VALID(port) REG_BIT(((port) - 1) * 4 + 0)
58 #define AUD_CONFIG_N_VALUE_INDEX REG_BIT(29)
59 #define AUD_CONFIG_N_PROG_ENABLE REG_BIT(28)
81 #define AUD_CONFIG_DISABLE_NCTS REG_BIT(3)
94 #define AUD_M_CTS_M_VALUE_INDEX REG_BIT(21)
95 #define AUD_M_CTS_M_PROG_ENABLE REG_BIT(20)
[all …]
H A Dintel_cursor_regs.h14 #define CURSOR_ENABLE REG_BIT(31)
15 #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
29 #define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26)
30 #define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
31 #define MCURSOR_ROTATE_180 REG_BIT(15)
32 #define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14)
48 #define CURSOR_POS_Y_SIGN REG_BIT(31)
51 #define CURSOR_POS_X_SIGN REG_BIT(15)
67 #define CUR_FBC_EN REG_BIT(31)
81 #define CUR_WM_EN REG_BIT(31)
[all …]
H A Dintel_pipe_crc_regs.h13 #define PIPE_CRC_ENABLE REG_BIT(31)
58 #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30)
59 #define PIPE_CRC_EXP_RED_MASK REG_BIT(22, 0) /* pre-ivb */
60 #define PIPE_CRC_EXP_1_MASK_IVB REG_BIT(22, 0) /* ivb */
64 #define PIPE_CRC_EXP_GREEN_MASK REG_BIT(22, 0) /* pre-ivb */
68 #define PIPE_CRC_EXP_BLUE_MASK REG_BIT(22, 0) /* pre-ivb */
72 #define PIPE_CRC_EXP_RES1_MASK REG_BIT(22, 0) /* pre-ivb */
76 #define PIPE_CRC_EXP_RES2_MASK REG_BIT(22, 0) /* pre-ivb */
97 #define PIPE_CRC_EXP_2_MASK_IVB REG_BIT(22, 0) /* ivb */
103 #define PIPE_CRC_EXP_3_MASK_IVB REG_BIT(22, 0) /* ivb */
[all …]
H A Dintel_lvds_regs.h17 #define LVDS_PORT_EN REG_BIT(31)
19 #define LVDS_PIPE_SEL_MASK REG_BIT(30)
24 #define LVDS_ENABLE_DITHER REG_BIT(25)
26 #define LVDS_VSYNC_POLARITY REG_BIT(21)
27 #define LVDS_HSYNC_POLARITY REG_BIT(20)
30 #define LVDS_BORDER_ENABLE REG_BIT(15)
63 #define LVDS_DETECTED REG_BIT(1)
H A Dintel_vdsc_regs.h24 #define VDSC0_ENABLE REG_BIT(31)
25 #define VDSC2_ENABLE REG_BIT(30)
26 #define SMALL_JOINER_CONFIG_3_ENGINES REG_BIT(23)
27 #define VDSC1_ENABLE REG_BIT(15)
42 #define ULTRA_JOINER_ENABLE REG_BIT(23)
43 #define PRIMARY_ULTRA_JOINER_ENABLE REG_BIT(22)
86 #define DSC_PPS0_NATIVE_422_ENABLE REG_BIT(23)
87 #define DSC_PPS0_NATIVE_420_ENABLE REG_BIT(22)
88 #define DSC_PPS0_ALT_ICH_SEL REG_BIT(20)
89 #define DSC_PPS0_VBR_ENABLE REG_BIT(19)
[all …]
H A Dintel_color_regs.h74 #define PRE_CSC_GAMMA_ENABLE REG_BIT(31) /* icl+ */
75 #define POST_CSC_GAMMA_ENABLE REG_BIT(30) /* icl+ */
76 #define PALETTE_ANTICOL_DISABLE REG_BIT(15) /* skl+ */
202 #define PAL_PREC_SPLIT_MODE REG_BIT(31)
203 #define PAL_PREC_AUTO_INCREMENT REG_BIT(15)
229 #define PRE_CSC_GAMC_AUTO_INCREMENT REG_BIT(10)
242 #define PAL_PREC_MULTI_SEG_AUTO_INCREMENT REG_BIT(15)
315 #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31)
316 #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
323 #define LUT_3D_ENABLE REG_BIT(31)
[all …]
H A Di9xx_wm_regs.h231 #define WM_LP_ENABLE REG_BIT(31)
245 #define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1S only */
/linux/drivers/gpu/drm/i915/
H A Di915_perf_oa_regs.h147 #define GEN12_OAM_BUFFER_MEMORY_SELECT REG_BIT(0) /* 0: PPGTT, 1: GGTT */
151 #define GEN12_OAM_CONTEXT_CONTROL_TIMER_ENABLE REG_BIT(1)
152 #define GEN12_OAM_CONTEXT_CONTROL_COUNTER_RESUME REG_BIT(0)
156 #define GEN12_OAM_CONTROL_COUNTER_ENABLE REG_BIT(0)
159 #define GEN12_OAM_DEBUG_BUFFER_SIZE_SELECT REG_BIT(12)
160 #define GEN12_OAM_DEBUG_INCLUDE_CLK_RATIO REG_BIT(6)
161 #define GEN12_OAM_DEBUG_DISABLE_CLK_RATIO_REPORTS REG_BIT(5)
162 #define GEN12_OAM_DEBUG_DISABLE_GO_1_0_REPORTS REG_BIT(2)
163 #define GEN12_OAM_DEBUG_DISABLE_CTX_SWITCH_REPORTS REG_BIT(1)
166 #define GEN12_OAM_STATUS_COUNTER_OVERFLOW REG_BIT(2)
[all …]
/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gpu_commands.h137 #define MI_STORE_QWORD_IMM_GEN8 (MI_INSTR(0x20, 3) | REG_BIT(21))
157 #define MI_LRI_LRM_CS_MMIO REG_BIT(19)
158 #define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
179 #define MI_LRR_SOURCE_CS_MMIO REG_BIT(18)
189 #define MI_BATCH_RESOURCE_STREAMER REG_BIT(10)
190 #define MI_BATCH_PREDICATE REG_BIT(15) /* HSW+ on RCS only*/
258 #define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)
259 #define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
310 #define PIPE_CONTROL0_HDC_PIPELINE_FLUSH REG_BIT(9) /* gen12 */
375 #define MFX_WAIT_DW0_MFX_SYNC_CONTROL_FLAG REG_BIT(8)
[all …]
/linux/drivers/net/ipa/
H A Dipa_table.c367 val = reg_bit(reg, IPV6_ROUTER_HASH); in ipa_table_hash_flush()
368 val |= reg_bit(reg, IPV6_FILTER_HASH); in ipa_table_hash_flush()
369 val |= reg_bit(reg, IPV4_ROUTER_HASH); in ipa_table_hash_flush()
370 val |= reg_bit(reg, IPV4_FILTER_HASH); in ipa_table_hash_flush()
375 val = reg_bit(reg, ROUTER_CACHE); in ipa_table_hash_flush()
376 val |= reg_bit(reg, FILTER_CACHE); in ipa_table_hash_flush()
H A Dipa_endpoint.c470 mask = reg_bit(reg, field_id); in ipa_endpoint_init_ctrl()
814 val |= reg_bit(reg, HDR_OFST_PKT_SIZE_VALID); in ipa_endpoint_init_hdr()
818 val |= reg_bit(reg, HDR_OFST_METADATA_VALID); in ipa_endpoint_init_hdr()
840 val |= reg_bit(reg, HDR_ENDIANNESS); /* big endian */ in ipa_endpoint_init_hdr_ext()
850 val |= reg_bit(reg, HDR_TOTAL_LEN_OR_PAD_VALID); in ipa_endpoint_init_hdr_ext()
852 val |= reg_bit(reg, HDR_PAYLOAD_LEN_INC_PADDING); in ipa_endpoint_init_hdr_ext()
1025 val |= reg_bit(reg, SW_EOF_ACTIVE); in ipa_endpoint_init_aggr()
1136 val = enable ? reg_bit(reg, HOL_BLOCK_EN) : 0; in ipa_endpoint_init_hol_block_en()
1281 val |= reg_bit(reg, STATUS_EN); in ipa_endpoint_status()
1647 val |= reg_bit(reg, ROUTE_DEF_HDR_TABLE); in ipa_endpoint_default_route_set()
[all …]
/linux/drivers/gpu/drm/i915/pxp/
H A Dintel_pxp_regs.h19 #define KCR_INIT_ALLOW_DISPLAY_ME_WRITES REG_BIT(14)
/linux/drivers/gpu/drm/xe/instructions/
H A Dxe_gsc_commands.h34 #define GSC_FW_LOAD_LIMIT_VALID REG_BIT(31)

12