1*df9f0ebeSVille Syrjälä /* SPDX-License-Identifier: MIT */ 2*df9f0ebeSVille Syrjälä /* 3*df9f0ebeSVille Syrjälä * Copyright © 2022 Intel Corporation 4*df9f0ebeSVille Syrjälä */ 5*df9f0ebeSVille Syrjälä 6*df9f0ebeSVille Syrjälä #ifndef __INTEL_DVO_REGS_H__ 7*df9f0ebeSVille Syrjälä #define __INTEL_DVO_REGS_H__ 8*df9f0ebeSVille Syrjälä 9*df9f0ebeSVille Syrjälä #include "intel_display_reg_defs.h" 10*df9f0ebeSVille Syrjälä 11*df9f0ebeSVille Syrjälä #define _DVOA 0x61120 12*df9f0ebeSVille Syrjälä #define _DVOB 0x61140 13*df9f0ebeSVille Syrjälä #define _DVOC 0x61160 14*df9f0ebeSVille Syrjälä #define DVO(port) _MMIO_PORT((port), _DVOA, _DVOB) 15*df9f0ebeSVille Syrjälä #define DVO_ENABLE REG_BIT(31) 16*df9f0ebeSVille Syrjälä #define DVO_PIPE_SEL_MASK REG_BIT(30) 17*df9f0ebeSVille Syrjälä #define DVO_PIPE_SEL(pipe) REG_FIELD_PREP(DVO_PIPE_SEL_MASK, (pipe)) 18*df9f0ebeSVille Syrjälä #define DVO_PIPE_STALL_MASK REG_GENMASK(29, 28) 19*df9f0ebeSVille Syrjälä #define DVO_PIPE_STALL_UNUSED REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 0) 20*df9f0ebeSVille Syrjälä #define DVO_PIPE_STALL REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 1) 21*df9f0ebeSVille Syrjälä #define DVO_PIPE_STALL_TV REG_FIELD_PREP(DVO_PIPE_STALL_MASK, 2) 22*df9f0ebeSVille Syrjälä #define DVO_INTERRUPT_SELECT REG_BIT(27) 23*df9f0ebeSVille Syrjälä #define DVO_DEDICATED_INT_ENABLE REG_BIT(26) 24*df9f0ebeSVille Syrjälä #define DVO_PRESERVE_MASK REG_GENMASK(25, 24) 25*df9f0ebeSVille Syrjälä #define DVO_USE_VGA_SYNC REG_BIT(15) 26*df9f0ebeSVille Syrjälä #define DVO_DATA_ORDER_MASK REG_BIT(14) 27*df9f0ebeSVille Syrjälä #define DVO_DATA_ORDER_I740 REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 0) 28*df9f0ebeSVille Syrjälä #define DVO_DATA_ORDER_FP REG_FIELD_PREP(DVO_DATA_ORDER_MASK, 1) 29*df9f0ebeSVille Syrjälä #define DVO_VSYNC_DISABLE REG_BIT(11) 30*df9f0ebeSVille Syrjälä #define DVO_HSYNC_DISABLE REG_BIT(10) 31*df9f0ebeSVille Syrjälä #define DVO_VSYNC_TRISTATE REG_BIT(9) 32*df9f0ebeSVille Syrjälä #define DVO_HSYNC_TRISTATE REG_BIT(8) 33*df9f0ebeSVille Syrjälä #define DVO_BORDER_ENABLE REG_BIT(7) 34*df9f0ebeSVille Syrjälä #define DVO_ACT_DATA_ORDER_MASK REG_BIT(6) 35*df9f0ebeSVille Syrjälä #define DVO_ACT_DATA_ORDER_RGGB REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0) 36*df9f0ebeSVille Syrjälä #define DVO_ACT_DATA_ORDER_GBRG REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1) 37*df9f0ebeSVille Syrjälä #define DVO_ACT_DATA_ORDER_GBRG_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 0) 38*df9f0ebeSVille Syrjälä #define DVO_ACT_DATA_ORDER_RGGB_ERRATA REG_FIELD_PREP(DVO_ACT_DATA_ORDER_MASK, 1) 39*df9f0ebeSVille Syrjälä #define DVO_VSYNC_ACTIVE_HIGH REG_BIT(4) 40*df9f0ebeSVille Syrjälä #define DVO_HSYNC_ACTIVE_HIGH REG_BIT(3) 41*df9f0ebeSVille Syrjälä #define DVO_BLANK_ACTIVE_HIGH REG_BIT(2) 42*df9f0ebeSVille Syrjälä #define DVO_OUTPUT_CSTATE_PIXELS REG_BIT(1) /* SDG only */ 43*df9f0ebeSVille Syrjälä #define DVO_OUTPUT_SOURCE_SIZE_PIXELS REG_BIT(0) /* SDG only */ 44*df9f0ebeSVille Syrjälä 45*df9f0ebeSVille Syrjälä #define _DVOA_SRCDIM 0x61124 46*df9f0ebeSVille Syrjälä #define _DVOB_SRCDIM 0x61144 47*df9f0ebeSVille Syrjälä #define _DVOC_SRCDIM 0x61164 48*df9f0ebeSVille Syrjälä #define DVO_SRCDIM(port) _MMIO_PORT((port), _DVOA_SRCDIM, _DVOB_SRCDIM) 49*df9f0ebeSVille Syrjälä #define DVO_SRCDIM_HORIZONTAL_MASK REG_GENMASK(22, 12) 50*df9f0ebeSVille Syrjälä #define DVO_SRCDIM_HORIZONTAL(x) REG_FIELD_PREP(DVO_SRCDIM_HORIZONTAL_MASK, (x)) 51*df9f0ebeSVille Syrjälä #define DVO_SRCDIM_VERTICAL_MASK REG_GENMASK(10, 0) 52*df9f0ebeSVille Syrjälä #define DVO_SRCDIM_VERTICAL(x) REG_FIELD_PREP(DVO_SRCDIM_VERTICAL_MASK, (x)) 53*df9f0ebeSVille Syrjälä 54*df9f0ebeSVille Syrjälä #endif /* __INTEL_DVO_REGS_H__ */ 55