1b79e8fd9SLucas De Marchi /* SPDX-License-Identifier: MIT */ 2b79e8fd9SLucas De Marchi /* 3b79e8fd9SLucas De Marchi * Copyright © 2023 Intel Corporation 4b79e8fd9SLucas De Marchi */ 5b79e8fd9SLucas De Marchi 6b79e8fd9SLucas De Marchi #ifndef _XE_ENGINE_REGS_H_ 7b79e8fd9SLucas De Marchi #define _XE_ENGINE_REGS_H_ 8b79e8fd9SLucas De Marchi 9b79e8fd9SLucas De Marchi #include <asm/page.h> 10b79e8fd9SLucas De Marchi 118cb49012SLucas De Marchi #include "regs/xe_reg_defs.h" 12b79e8fd9SLucas De Marchi 13f52e4e90SMatt Roper /* 14f52e4e90SMatt Roper * These *_BASE values represent the MMIO offset where each hardware engine's 15f52e4e90SMatt Roper * registers start. The other definitions in this header are parameterized 16f52e4e90SMatt Roper * macros that will take one of these values as a parameter. 17f52e4e90SMatt Roper */ 18f52e4e90SMatt Roper #define RENDER_RING_BASE 0x02000 19f52e4e90SMatt Roper #define BSD_RING_BASE 0x1c0000 20f52e4e90SMatt Roper #define BSD2_RING_BASE 0x1c4000 21f52e4e90SMatt Roper #define BSD3_RING_BASE 0x1d0000 22f52e4e90SMatt Roper #define BSD4_RING_BASE 0x1d4000 23f52e4e90SMatt Roper #define XEHP_BSD5_RING_BASE 0x1e0000 24f52e4e90SMatt Roper #define XEHP_BSD6_RING_BASE 0x1e4000 25f52e4e90SMatt Roper #define XEHP_BSD7_RING_BASE 0x1f0000 26f52e4e90SMatt Roper #define XEHP_BSD8_RING_BASE 0x1f4000 27f52e4e90SMatt Roper #define VEBOX_RING_BASE 0x1c8000 28f52e4e90SMatt Roper #define VEBOX2_RING_BASE 0x1d8000 29f52e4e90SMatt Roper #define XEHP_VEBOX3_RING_BASE 0x1e8000 30f52e4e90SMatt Roper #define XEHP_VEBOX4_RING_BASE 0x1f8000 31f52e4e90SMatt Roper #define COMPUTE0_RING_BASE 0x1a000 32f52e4e90SMatt Roper #define COMPUTE1_RING_BASE 0x1c000 33f52e4e90SMatt Roper #define COMPUTE2_RING_BASE 0x1e000 34f52e4e90SMatt Roper #define COMPUTE3_RING_BASE 0x26000 35f52e4e90SMatt Roper #define BLT_RING_BASE 0x22000 36f52e4e90SMatt Roper #define XEHPC_BCS1_RING_BASE 0x3e0000 37f52e4e90SMatt Roper #define XEHPC_BCS2_RING_BASE 0x3e2000 38f52e4e90SMatt Roper #define XEHPC_BCS3_RING_BASE 0x3e4000 39f52e4e90SMatt Roper #define XEHPC_BCS4_RING_BASE 0x3e6000 40f52e4e90SMatt Roper #define XEHPC_BCS5_RING_BASE 0x3e8000 41f52e4e90SMatt Roper #define XEHPC_BCS6_RING_BASE 0x3ea000 42f52e4e90SMatt Roper #define XEHPC_BCS7_RING_BASE 0x3ec000 43f52e4e90SMatt Roper #define XEHPC_BCS8_RING_BASE 0x3ee000 44f52e4e90SMatt Roper #define GSCCS_RING_BASE 0x11a000 45f52e4e90SMatt Roper 463512a78aSLucas De Marchi #define RING_TAIL(base) XE_REG((base) + 0x30) 4785cfc412SNiranjana Vishwanathapura #define TAIL_ADDR REG_GENMASK(20, 3) 48b79e8fd9SLucas De Marchi 493512a78aSLucas De Marchi #define RING_HEAD(base) XE_REG((base) + 0x34) 5085cfc412SNiranjana Vishwanathapura #define HEAD_ADDR REG_GENMASK(20, 2) 51b79e8fd9SLucas De Marchi 523512a78aSLucas De Marchi #define RING_START(base) XE_REG((base) + 0x38) 53b79e8fd9SLucas De Marchi 543512a78aSLucas De Marchi #define RING_CTL(base) XE_REG((base) + 0x3c) 55b79e8fd9SLucas De Marchi #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ 56b79e8fd9SLucas De Marchi #define RING_CTL_SIZE(size) ((size) - PAGE_SIZE) /* in bytes -> pages */ 57b79e8fd9SLucas De Marchi 587578c2f8SNiranjana Vishwanathapura #define RING_START_UDW(base) XE_REG((base) + 0x48) 597578c2f8SNiranjana Vishwanathapura 60ca2acce7SLucas De Marchi #define RING_PSMI_CTL(base) XE_REG((base) + 0x50, XE_REG_OPTION_MASKED) 61d9b79ad2SLucas De Marchi #define RC_SEMA_IDLE_MSG_DISABLE REG_BIT(12) 62d9b79ad2SLucas De Marchi #define WAIT_FOR_EVENT_POWER_DOWN_DISABLE REG_BIT(7) 6307d7ba13SDaniele Ceraolo Spurio #define IDLE_MSG_DISABLE REG_BIT(0) 6407d7ba13SDaniele Ceraolo Spurio 6507d7ba13SDaniele Ceraolo Spurio #define RING_PWRCTX_MAXCNT(base) XE_REG((base) + 0x54) 6607d7ba13SDaniele Ceraolo Spurio #define IDLE_WAIT_TIME REG_GENMASK(19, 0) 67b79e8fd9SLucas De Marchi 683512a78aSLucas De Marchi #define RING_ACTHD_UDW(base) XE_REG((base) + 0x5c) 693512a78aSLucas De Marchi #define RING_DMA_FADD_UDW(base) XE_REG((base) + 0x60) 703512a78aSLucas De Marchi #define RING_IPEHR(base) XE_REG((base) + 0x68) 71c8d4524eSJosé Roberto de Souza #define RING_INSTDONE(base) XE_REG((base) + 0x6c) 723512a78aSLucas De Marchi #define RING_ACTHD(base) XE_REG((base) + 0x74) 733512a78aSLucas De Marchi #define RING_DMA_FADD(base) XE_REG((base) + 0x78) 743512a78aSLucas De Marchi #define RING_HWS_PGA(base) XE_REG((base) + 0x80) 753512a78aSLucas De Marchi #define RING_HWSTAM(base) XE_REG((base) + 0x98) 763512a78aSLucas De Marchi #define RING_MI_MODE(base) XE_REG((base) + 0x9c) 773512a78aSLucas De Marchi #define RING_NOPID(base) XE_REG((base) + 0x94) 78b79e8fd9SLucas De Marchi 795ea7fe65SMatt Roper #define FF_THREAD_MODE(base) XE_REG((base) + 0xa0) 805ea7fe65SMatt Roper #define FF_TESSELATION_DOP_GATE_DISABLE BIT(19) 815ea7fe65SMatt Roper 8254020e2bSMichal Wajdeczko #define RING_INT_SRC_RPT_PTR(base) XE_REG((base) + 0xa4) 833512a78aSLucas De Marchi #define RING_IMR(base) XE_REG((base) + 0xa8) 8454020e2bSMichal Wajdeczko #define RING_INT_STATUS_RPT_PTR(base) XE_REG((base) + 0xac) 85b79e8fd9SLucas De Marchi 863512a78aSLucas De Marchi #define RING_EIR(base) XE_REG((base) + 0xb0) 873512a78aSLucas De Marchi #define RING_EMR(base) XE_REG((base) + 0xb4) 883512a78aSLucas De Marchi #define RING_ESR(base) XE_REG((base) + 0xb8) 89e3ec5e75SJosé Roberto de Souza 90570a8fc2SLucas De Marchi #define INSTPM(base) XE_REG((base) + 0xc0, XE_REG_OPTION_MASKED) 91570a8fc2SLucas De Marchi #define ENABLE_SEMAPHORE_POLL_BIT REG_BIT(13) 92570a8fc2SLucas De Marchi 93e3ec5e75SJosé Roberto de Souza #define RING_CMD_CCTL(base) XE_REG((base) + 0xc4, XE_REG_OPTION_MASKED) 94e3ec5e75SJosé Roberto de Souza /* 95e3ec5e75SJosé Roberto de Souza * CMD_CCTL read/write fields take a MOCS value and _not_ a table index. 96e3ec5e75SJosé Roberto de Souza * The lsb of each can be considered a separate enabling bit for encryption. 97e3ec5e75SJosé Roberto de Souza * 6:0 == default MOCS value for reads => 6:1 == table index for reads. 98e3ec5e75SJosé Roberto de Souza * 13:7 == default MOCS value for writes => 13:8 == table index for writes. 99e3ec5e75SJosé Roberto de Souza * 15:14 == Reserved => 31:30 are set to 0. 100e3ec5e75SJosé Roberto de Souza */ 101e3ec5e75SJosé Roberto de Souza #define CMD_CCTL_WRITE_OVERRIDE_MASK REG_GENMASK(13, 8) 102e3ec5e75SJosé Roberto de Souza #define CMD_CCTL_READ_OVERRIDE_MASK REG_GENMASK(6, 1) 103e3ec5e75SJosé Roberto de Souza 104bc17ec0bSMatt Roper #define CSFE_CHICKEN1(base) XE_REG((base) + 0xd4, XE_REG_OPTION_MASKED) 105bc17ec0bSMatt Roper #define GHWSP_CSB_REPORT_DIS REG_BIT(15) 106bc17ec0bSMatt Roper #define PPHWSP_CSB_AND_TIMESTAMP_REPORT_DIS REG_BIT(14) 107bc17ec0bSMatt Roper 1085ea7fe65SMatt Roper #define FF_SLICE_CS_CHICKEN1(base) XE_REG((base) + 0xe0, XE_REG_OPTION_MASKED) 1095ea7fe65SMatt Roper #define FFSC_PERCTX_PREEMPT_CTRL REG_BIT(14) 1105ea7fe65SMatt Roper 1115ea7fe65SMatt Roper #define CS_DEBUG_MODE1(base) XE_REG((base) + 0xec, XE_REG_OPTION_MASKED) 1125ea7fe65SMatt Roper #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1) 1135ea7fe65SMatt Roper #define REPLAY_MODE_GRANULARITY REG_BIT(0) 1145ea7fe65SMatt Roper 1157578c2f8SNiranjana Vishwanathapura #define INDIRECT_RING_STATE(base) XE_REG((base) + 0x108) 1167578c2f8SNiranjana Vishwanathapura 1173512a78aSLucas De Marchi #define RING_BBADDR(base) XE_REG((base) + 0x140) 1183512a78aSLucas De Marchi #define RING_BBADDR_UDW(base) XE_REG((base) + 0x168) 119bb95a4f9SJosé Roberto de Souza 12025063811SNiranjana Vishwanathapura #define BCS_SWCTRL(base) XE_REG((base) + 0x200, XE_REG_OPTION_MASKED) 1217407f2e5SNiranjana Vishwanathapura #define BCS_SWCTRL_DISABLE_256B REG_BIT(2) 12225063811SNiranjana Vishwanathapura 123bb95a4f9SJosé Roberto de Souza /* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */ 124bb95a4f9SJosé Roberto de Souza #define BLIT_CCTL(base) XE_REG((base) + 0x204) 125bb95a4f9SJosé Roberto de Souza #define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 9) 126bb95a4f9SJosé Roberto de Souza #define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 1) 127bb95a4f9SJosé Roberto de Souza 1283512a78aSLucas De Marchi #define RING_EXECLIST_STATUS_LO(base) XE_REG((base) + 0x234) 1293512a78aSLucas De Marchi #define RING_EXECLIST_STATUS_HI(base) XE_REG((base) + 0x234 + 4) 130b79e8fd9SLucas De Marchi 131dc30c6e7SAshutosh Dixit #define RING_CONTEXT_CONTROL(base) XE_REG((base) + 0x244, XE_REG_OPTION_MASKED) 1322f4a730fSAshutosh Dixit #define CTX_CTRL_OAC_CONTEXT_ENABLE REG_BIT(8) 133*14e077f8SAshutosh Dixit #define CTX_CTRL_RUN_ALONE REG_BIT(7) 134d6219e1cSNiranjana Vishwanathapura #define CTX_CTRL_INDIRECT_RING_STATE_ENABLE REG_BIT(4) 135b79e8fd9SLucas De Marchi #define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH REG_BIT(3) 136b79e8fd9SLucas De Marchi #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT REG_BIT(0) 137b79e8fd9SLucas De Marchi 1383512a78aSLucas De Marchi #define RING_MODE(base) XE_REG((base) + 0x29c) 1395f230a14SLucas De Marchi #define GFX_DISABLE_LEGACY_MODE REG_BIT(3) 140b79e8fd9SLucas De Marchi 1413512a78aSLucas De Marchi #define RING_TIMESTAMP(base) XE_REG((base) + 0x358) 142b79e8fd9SLucas De Marchi 1433512a78aSLucas De Marchi #define RING_TIMESTAMP_UDW(base) XE_REG((base) + 0x358 + 4) 144b79e8fd9SLucas De Marchi #define RING_VALID_MASK 0x00000001 145b79e8fd9SLucas De Marchi #define RING_VALID 0x00000001 146b79e8fd9SLucas De Marchi #define STOP_RING REG_BIT(8) 147b79e8fd9SLucas De Marchi 1483512a78aSLucas De Marchi #define RING_CTX_TIMESTAMP(base) XE_REG((base) + 0x3a8) 149570a8fc2SLucas De Marchi #define CSBE_DEBUG_STATUS(base) XE_REG((base) + 0x3fc) 150b79e8fd9SLucas De Marchi 1513512a78aSLucas De Marchi #define RING_FORCE_TO_NONPRIV(base, i) XE_REG(((base) + 0x4d0) + (i) * 4) 152b79e8fd9SLucas De Marchi #define RING_FORCE_TO_NONPRIV_DENY REG_BIT(30) 1535f230a14SLucas De Marchi #define RING_FORCE_TO_NONPRIV_ACCESS_MASK REG_GENMASK(29, 28) 1545f230a14SLucas De Marchi #define RING_FORCE_TO_NONPRIV_ACCESS_RW REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 0) 1555f230a14SLucas De Marchi #define RING_FORCE_TO_NONPRIV_ACCESS_RD REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 1) 1565f230a14SLucas De Marchi #define RING_FORCE_TO_NONPRIV_ACCESS_WR REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 2) 1575f230a14SLucas De Marchi #define RING_FORCE_TO_NONPRIV_ACCESS_INVALID REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_ACCESS_MASK, 3) 158b79e8fd9SLucas De Marchi #define RING_FORCE_TO_NONPRIV_ADDRESS_MASK REG_GENMASK(25, 2) 1595f230a14SLucas De Marchi #define RING_FORCE_TO_NONPRIV_RANGE_MASK REG_GENMASK(1, 0) 1605f230a14SLucas De Marchi #define RING_FORCE_TO_NONPRIV_RANGE_1 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 0) 1615f230a14SLucas De Marchi #define RING_FORCE_TO_NONPRIV_RANGE_4 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 1) 1625f230a14SLucas De Marchi #define RING_FORCE_TO_NONPRIV_RANGE_16 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 2) 1635f230a14SLucas De Marchi #define RING_FORCE_TO_NONPRIV_RANGE_64 REG_FIELD_PREP(RING_FORCE_TO_NONPRIV_RANGE_MASK, 3) 164b79e8fd9SLucas De Marchi #define RING_FORCE_TO_NONPRIV_MASK_VALID (RING_FORCE_TO_NONPRIV_RANGE_MASK | \ 165b79e8fd9SLucas De Marchi RING_FORCE_TO_NONPRIV_ACCESS_MASK | \ 166b79e8fd9SLucas De Marchi RING_FORCE_TO_NONPRIV_DENY) 167b79e8fd9SLucas De Marchi #define RING_MAX_NONPRIV_SLOTS 12 168b79e8fd9SLucas De Marchi 1693512a78aSLucas De Marchi #define RING_EXECLIST_SQ_CONTENTS_LO(base) XE_REG((base) + 0x510) 1703512a78aSLucas De Marchi #define RING_EXECLIST_SQ_CONTENTS_HI(base) XE_REG((base) + 0x510 + 4) 171b79e8fd9SLucas De Marchi 1723512a78aSLucas De Marchi #define RING_EXECLIST_CONTROL(base) XE_REG((base) + 0x550) 173b79e8fd9SLucas De Marchi #define EL_CTRL_LOAD REG_BIT(0) 174b79e8fd9SLucas De Marchi 1755ea7fe65SMatt Roper #define CS_CHICKEN1(base) XE_REG((base) + 0x580, XE_REG_OPTION_MASKED) 1765ea7fe65SMatt Roper #define PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1)) 1775ea7fe65SMatt Roper #define PREEMPT_GPGPU_MID_THREAD_LEVEL PREEMPT_GPGPU_LEVEL(0, 0) 1785ea7fe65SMatt Roper #define PREEMPT_GPGPU_THREAD_GROUP_LEVEL PREEMPT_GPGPU_LEVEL(0, 1) 1795ea7fe65SMatt Roper #define PREEMPT_GPGPU_COMMAND_LEVEL PREEMPT_GPGPU_LEVEL(1, 0) 1805ea7fe65SMatt Roper #define PREEMPT_GPGPU_LEVEL_MASK PREEMPT_GPGPU_LEVEL(1, 1) 1815ea7fe65SMatt Roper #define PREEMPT_3D_OBJECT_LEVEL REG_BIT(0) 1825ea7fe65SMatt Roper 1838bfbe174STejas Upadhyay #define VDBOX_CGCTL3F08(base) XE_REG((base) + 0x3f08) 1848bfbe174STejas Upadhyay #define CG3DDISHRS_CLKGATE_DIS REG_BIT(5) 1858bfbe174STejas Upadhyay 1863512a78aSLucas De Marchi #define VDBOX_CGCTL3F10(base) XE_REG((base) + 0x3f10) 187b79e8fd9SLucas De Marchi #define IECPUNIT_CLKGATE_DIS REG_BIT(22) 188b79e8fd9SLucas De Marchi 1893512a78aSLucas De Marchi #define VDBOX_CGCTL3F18(base) XE_REG((base) + 0x3f18) 190b79e8fd9SLucas De Marchi #define ALNUNIT_CLKGATE_DIS REG_BIT(13) 191b79e8fd9SLucas De Marchi 1926ffef7b6SGustavo Sousa #define VDBOX_CGCTL3F1C(base) XE_REG((base) + 0x3f1c) 1936ffef7b6SGustavo Sousa #define MFXPIPE_CLKGATE_DIS REG_BIT(3) 1946ffef7b6SGustavo Sousa 195b79e8fd9SLucas De Marchi #endif 196