1226bfec8SLucas De Marchi /* SPDX-License-Identifier: MIT */ 2226bfec8SLucas De Marchi /* 3226bfec8SLucas De Marchi * Copyright © 2023 Intel Corporation 4226bfec8SLucas De Marchi */ 5226bfec8SLucas De Marchi 6226bfec8SLucas De Marchi #ifndef _XE_GT_REGS_H_ 7226bfec8SLucas De Marchi #define _XE_GT_REGS_H_ 8226bfec8SLucas De Marchi 98cb49012SLucas De Marchi #include "regs/xe_reg_defs.h" 10226bfec8SLucas De Marchi 117bfbad97SMatt Roper /* 127bfbad97SMatt Roper * The GSI register range [0x0 - 0x40000) is replicated at a higher offset 137bfbad97SMatt Roper * for the media GT. xe_mmio and xe_gt_mcr functions will automatically 147bfbad97SMatt Roper * translate offsets by MEDIA_GT_GSI_OFFSET when operating on the media GT. 157bfbad97SMatt Roper */ 167bfbad97SMatt Roper #define MEDIA_GT_GSI_OFFSET 0x380000 177bfbad97SMatt Roper #define MEDIA_GT_GSI_LENGTH 0x40000 187bfbad97SMatt Roper 197b076d14SBadal Nilawar /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ 207b076d14SBadal Nilawar #define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60) 217b076d14SBadal Nilawar #define MTL_CAGF_MASK REG_GENMASK(8, 0) 227b076d14SBadal Nilawar #define MTL_CC_MASK REG_GENMASK(12, 9) 237b076d14SBadal Nilawar 24226bfec8SLucas De Marchi /* RPM unit config (Gen8+) */ 253512a78aSLucas De Marchi #define RPM_CONFIG0 XE_REG(0xd00) 265f230a14SLucas De Marchi #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK REG_GENMASK(5, 3) 27d9b79ad2SLucas De Marchi #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 28d9b79ad2SLucas De Marchi #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 29d9b79ad2SLucas De Marchi #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 30d9b79ad2SLucas De Marchi #define RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 315f230a14SLucas De Marchi #define RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) 32226bfec8SLucas De Marchi 333512a78aSLucas De Marchi #define FORCEWAKE_ACK_MEDIA_VDBOX(n) XE_REG(0xd50 + (n) * 4) 343512a78aSLucas De Marchi #define FORCEWAKE_ACK_MEDIA_VEBOX(n) XE_REG(0xd70 + (n) * 4) 353512a78aSLucas De Marchi #define FORCEWAKE_ACK_RENDER XE_REG(0xd84) 365822bba9SMatt Roper 373512a78aSLucas De Marchi #define GMD_ID XE_REG(0xd8c) 385822bba9SMatt Roper #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22) 395822bba9SMatt Roper #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) 406ed6ba32SMatt Roper #define GMD_ID_REVID REG_GENMASK(5, 0) 415822bba9SMatt Roper 42f4c33ae8SDaniele Ceraolo Spurio #define FORCEWAKE_ACK_GSC XE_REG(0xdf8) 433512a78aSLucas De Marchi #define FORCEWAKE_ACK_GT_MTL XE_REG(0xdfc) 44226bfec8SLucas De Marchi 453512a78aSLucas De Marchi #define MCFG_MCR_SELECTOR XE_REG(0xfd0) 463512a78aSLucas De Marchi #define MTL_MCR_SELECTOR XE_REG(0xfd4) 473512a78aSLucas De Marchi #define SF_MCR_SELECTOR XE_REG(0xfd8) 483512a78aSLucas De Marchi #define MCR_SELECTOR XE_REG(0xfdc) 493512a78aSLucas De Marchi #define GAM_MCR_SELECTOR XE_REG(0xfe0) 50d9b79ad2SLucas De Marchi #define MCR_MULTICAST REG_BIT(31) 515f230a14SLucas De Marchi #define MCR_SLICE_MASK REG_GENMASK(30, 27) 525f230a14SLucas De Marchi #define MCR_SLICE(slice) REG_FIELD_PREP(MCR_SLICE_MASK, slice) 535f230a14SLucas De Marchi #define MCR_SUBSLICE_MASK REG_GENMASK(26, 24) 545f230a14SLucas De Marchi #define MCR_SUBSLICE(subslice) REG_FIELD_PREP(MCR_SUBSLICE_MASK, subslice) 55226bfec8SLucas De Marchi #define MTL_MCR_GROUPID REG_GENMASK(11, 8) 56226bfec8SLucas De Marchi #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0) 57226bfec8SLucas De Marchi 583512a78aSLucas De Marchi #define PS_INVOCATION_COUNT XE_REG(0x2348) 59226bfec8SLucas De Marchi 6083af834eSMatt Roper #define XELP_GLOBAL_MOCS(i) XE_REG(0x4000 + (i) * 4) 6183af834eSMatt Roper #define XEHP_GLOBAL_MOCS(i) XE_REG_MCR(0x4000 + (i) * 4) 629fbd0adbSJanga Rahul Kumar #define LE_SSE_MASK REG_GENMASK(18, 17) 639fbd0adbSJanga Rahul Kumar #define LE_SSE(value) REG_FIELD_PREP(LE_SSE_MASK, value) 649fbd0adbSJanga Rahul Kumar #define LE_COS_MASK REG_GENMASK(16, 15) 659fbd0adbSJanga Rahul Kumar #define LE_COS(value) REG_FIELD_PREP(LE_COS_MASK) 669fbd0adbSJanga Rahul Kumar #define LE_SCF_MASK REG_BIT(14) 679fbd0adbSJanga Rahul Kumar #define LE_SCF(value) REG_FIELD_PREP(LE_SCF_MASK, value) 689fbd0adbSJanga Rahul Kumar #define LE_PFM_MASK REG_GENMASK(13, 11) 699fbd0adbSJanga Rahul Kumar #define LE_PFM(value) REG_FIELD_PREP(LE_PFM_MASK, value) 709fbd0adbSJanga Rahul Kumar #define LE_SCC_MASK REG_GENMASK(10, 8) 719fbd0adbSJanga Rahul Kumar #define LE_SCC(value) REG_FIELD_PREP(LE_SCC_MASK, value) 729fbd0adbSJanga Rahul Kumar #define LE_RSC_MASK REG_BIT(7) 739fbd0adbSJanga Rahul Kumar #define LE_RSC(value) REG_FIELD_PREP(LE_RSC_MASK, value) 749fbd0adbSJanga Rahul Kumar #define LE_AOM_MASK REG_BIT(6) 759fbd0adbSJanga Rahul Kumar #define LE_AOM(value) REG_FIELD_PREP(LE_AOM_MASK, value) 769fbd0adbSJanga Rahul Kumar #define LE_LRUM_MASK REG_GENMASK(5, 4) 779fbd0adbSJanga Rahul Kumar #define LE_LRUM(value) REG_FIELD_PREP(LE_LRUM_MASK, value) 789fbd0adbSJanga Rahul Kumar #define LE_TGT_CACHE_MASK REG_GENMASK(3, 2) 799fbd0adbSJanga Rahul Kumar #define LE_TGT_CACHE(value) REG_FIELD_PREP(LE_TGT_CACHE_MASK, value) 809fbd0adbSJanga Rahul Kumar #define LE_CACHEABILITY_MASK REG_GENMASK(1, 0) 819fbd0adbSJanga Rahul Kumar #define LE_CACHEABILITY(value) REG_FIELD_PREP(LE_CACHEABILITY_MASK, value) 829fbd0adbSJanga Rahul Kumar 834551d602STejas Upadhyay #define STATELESS_COMPRESSION_CTRL XE_REG_MCR(0x4148) 84ecabb5e6SShekhar Chauhan #define UNIFIED_COMPRESSION_FORMAT REG_GENMASK(3, 0) 85ecabb5e6SShekhar Chauhan 86f0ffa657STejas Upadhyay #define XE2_GAMREQSTRM_CTRL XE_REG_MCR(0x4194) 8701570b44SMatthew Auld #define CG_DIS_CNTLBUS REG_BIT(6) 8801570b44SMatthew Auld 893512a78aSLucas De Marchi #define CCS_AUX_INV XE_REG(0x4208) 90226bfec8SLucas De Marchi 913512a78aSLucas De Marchi #define VD0_AUX_INV XE_REG(0x4218) 923512a78aSLucas De Marchi #define VE0_AUX_INV XE_REG(0x4238) 93226bfec8SLucas De Marchi 943512a78aSLucas De Marchi #define VE1_AUX_INV XE_REG(0x42b8) 95226bfec8SLucas De Marchi #define AUX_INV REG_BIT(0) 96226bfec8SLucas De Marchi 97466a6c38SMichal Wajdeczko #define XE2_LMEM_CFG XE_REG(0x48b0) 98466a6c38SMichal Wajdeczko 9961f288a8SMichael J. Ruhl #define XEHP_TILE_ADDR_RANGE(_idx) XE_REG_MCR(0x4900 + (_idx) * 4) 1003512a78aSLucas De Marchi #define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910) 101b5c2ca03SHimal Prasad Ghimiray #define XEHP_FLAT_CCS_PTR REG_GENMASK(31, 8) 102226bfec8SLucas De Marchi 103a409901fSTejas Upadhyay #define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED) 104a409901fSTejas Upadhyay #define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10) 105a409901fSTejas Upadhyay 1067f3ee7d8SHaridhar Kalvala #define CHICKEN_RASTER_1 XE_REG_MCR(0x6204, XE_REG_OPTION_MASKED) 1077f3ee7d8SHaridhar Kalvala #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8) 108*da9a73b7STejas Upadhyay #define DIS_CLIP_NEGATIVE_BOUNDING_BOX REG_BIT(6) 1097f3ee7d8SHaridhar Kalvala 110ca2acce7SLucas De Marchi #define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED) 11111f78b13SLucas De Marchi #define TBIMR_FAST_CLIP REG_BIT(5) 11211f78b13SLucas De Marchi 113bad3644dSDnyaneshwar Bhadane #define FF_MODE XE_REG_MCR(0x6210) 114bad3644dSDnyaneshwar Bhadane #define DIS_TE_AUTOSTRIP REG_BIT(31) 115e4ac526cSSai Teja Pottumuttu #define VS_HIT_MAX_VALUE_MASK REG_GENMASK(25, 20) 116bad3644dSDnyaneshwar Bhadane #define DIS_MESH_PARTIAL_AUTOSTRIP REG_BIT(16) 117bad3644dSDnyaneshwar Bhadane #define DIS_MESH_AUTOSTRIP REG_BIT(15) 118bad3644dSDnyaneshwar Bhadane 119ca2acce7SLucas De Marchi #define VFLSKPD XE_REG_MCR(0x62a8, XE_REG_OPTION_MASKED) 120bad3644dSDnyaneshwar Bhadane #define DIS_PARTIAL_AUTOSTRIP REG_BIT(9) 121bad3644dSDnyaneshwar Bhadane #define DIS_AUTOSTRIP REG_BIT(6) 1228cd7e975SLucas De Marchi #define DIS_OVER_FETCH_CACHE REG_BIT(1) 1238cd7e975SLucas De Marchi #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) 1248cd7e975SLucas De Marchi 1253512a78aSLucas De Marchi #define FF_MODE2 XE_REG(0x6604) 1263512a78aSLucas De Marchi #define XEHP_FF_MODE2 XE_REG_MCR(0x6604) 127226bfec8SLucas De Marchi #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) 128226bfec8SLucas De Marchi #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) 129226bfec8SLucas De Marchi #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) 130226bfec8SLucas De Marchi #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) 131226bfec8SLucas De Marchi 132c8d4524eSJosé Roberto de Souza #define XEHPG_INSTDONE_GEOM_SVGUNIT XE_REG_MCR(0x666c) 133c8d4524eSJosé Roberto de Souza 134ca2acce7SLucas De Marchi #define CACHE_MODE_1 XE_REG(0x7004, XE_REG_OPTION_MASKED) 1358cd7e975SLucas De Marchi #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) 1368cd7e975SLucas De Marchi 1379f18b55bSHimal Prasad Ghimiray #define COMMON_SLICE_CHICKEN1 XE_REG(0x7010, XE_REG_OPTION_MASKED) 1389f18b55bSHimal Prasad Ghimiray #define DISABLE_BOTTOM_CLIP_RECTANGLE_TEST REG_BIT(14) 139aaa536a8SMatt Roper 140aaa536a8SMatt Roper #define HIZ_CHICKEN XE_REG(0x7018, XE_REG_OPTION_MASKED) 141aaa536a8SMatt Roper #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14) 142aaa536a8SMatt Roper #define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13) 143aaa536a8SMatt Roper 144ca2acce7SLucas De Marchi #define XEHP_PSS_MODE2 XE_REG_MCR(0x703c, XE_REG_OPTION_MASKED) 1458cd7e975SLucas De Marchi #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) 1468cd7e975SLucas De Marchi 147bad3644dSDnyaneshwar Bhadane #define XEHP_PSS_CHICKEN XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED) 1486a1fd678STejas Upadhyay #define FLSH_IGNORES_PSD REG_BIT(10) 149bad3644dSDnyaneshwar Bhadane #define FD_END_COLLECT REG_BIT(5) 150bad3644dSDnyaneshwar Bhadane 151c8d4524eSJosé Roberto de Souza #define SC_INSTDONE XE_REG(0x7100) 152c8d4524eSJosé Roberto de Souza #define SC_INSTDONE_EXTRA XE_REG(0x7104) 153c8d4524eSJosé Roberto de Souza #define SC_INSTDONE_EXTRA2 XE_REG(0x7108) 154c8d4524eSJosé Roberto de Souza 155c8d4524eSJosé Roberto de Souza #define XEHPG_SC_INSTDONE XE_REG_MCR(0x7100) 156c8d4524eSJosé Roberto de Souza #define XEHPG_SC_INSTDONE_EXTRA XE_REG_MCR(0x7104) 157c8d4524eSJosé Roberto de Souza #define XEHPG_SC_INSTDONE_EXTRA2 XE_REG_MCR(0x7108) 158c8d4524eSJosé Roberto de Souza 159ca2acce7SLucas De Marchi #define COMMON_SLICE_CHICKEN4 XE_REG(0x7300, XE_REG_OPTION_MASKED) 160fd93946dSLucas De Marchi #define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) 161fd93946dSLucas De Marchi 162ca2acce7SLucas De Marchi #define COMMON_SLICE_CHICKEN3 XE_REG(0x7304, XE_REG_OPTION_MASKED) 163ca2acce7SLucas De Marchi #define XEHP_COMMON_SLICE_CHICKEN3 XE_REG_MCR(0x7304, XE_REG_OPTION_MASKED) 164226bfec8SLucas De Marchi #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) 165226bfec8SLucas De Marchi #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12) 166d9b79ad2SLucas De Marchi #define BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) 167d9b79ad2SLucas De Marchi #define DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) 168226bfec8SLucas De Marchi 169ca2acce7SLucas De Marchi #define XEHP_SLICE_COMMON_ECO_CHICKEN1 XE_REG_MCR(0x731c, XE_REG_OPTION_MASKED) 1708cd7e975SLucas De Marchi #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) 1718cd7e975SLucas De Marchi 172ca2acce7SLucas De Marchi #define VF_PREEMPTION XE_REG(0x83a4, XE_REG_OPTION_MASKED) 1738cd7e975SLucas De Marchi #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) 1748cd7e975SLucas De Marchi 175bad3644dSDnyaneshwar Bhadane #define VF_SCRATCHPAD XE_REG(0x83a8, XE_REG_OPTION_MASKED) 176bad3644dSDnyaneshwar Bhadane #define XE2_VFG_TED_CREDIT_INTERFACE_DISABLE REG_BIT(13) 177bad3644dSDnyaneshwar Bhadane 178ca2acce7SLucas De Marchi #define VFG_PREEMPTION_CHICKEN XE_REG(0x83b4, XE_REG_OPTION_MASKED) 1794d5ab121SLucas De Marchi #define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4) 1804d5ab121SLucas De Marchi 181ff063430SMatt Roper #define SQCNT1 XE_REG_MCR(0x8718) 1827eea3fb6SShekhar Chauhan #define XELPMP_SQCNT1 XE_REG(0x8718) 1831db9a9dcSAshutosh Dixit #define SQCNT1_PMON_ENABLE REG_BIT(30) 1841db9a9dcSAshutosh Dixit #define SQCNT1_OABPC REG_BIT(29) 185ff063430SMatt Roper #define ENFORCE_RAR REG_BIT(23) 186ff063430SMatt Roper 1873512a78aSLucas De Marchi #define XEHP_SQCM XE_REG_MCR(0x8724) 188226bfec8SLucas De Marchi #define EN_32B_ACCESS REG_BIT(30) 189226bfec8SLucas De Marchi 1904cb12b71SHimal Prasad Ghimiray #define XE2_FLAT_CCS_BASE_RANGE_LOWER XE_REG_MCR(0x8800) 1914cb12b71SHimal Prasad Ghimiray #define XE2_FLAT_CCS_ENABLE REG_BIT(0) 192b5c2ca03SHimal Prasad Ghimiray #define XE2_FLAT_CCS_BASE_LOWER_ADDR_MASK REG_GENMASK(31, 6) 193b5c2ca03SHimal Prasad Ghimiray 194b5c2ca03SHimal Prasad Ghimiray #define XE2_FLAT_CCS_BASE_RANGE_UPPER XE_REG_MCR(0x8804) 195b5c2ca03SHimal Prasad Ghimiray #define XE2_FLAT_CCS_BASE_UPPER_ADDR_MASK REG_GENMASK(7, 0) 1964cb12b71SHimal Prasad Ghimiray 1975d30cfe0SMatt Roper #define GSCPSMI_BASE XE_REG(0x880c) 1985d30cfe0SMatt Roper 19902c4e64aSShekhar Chauhan #define CCCHKNREG1 XE_REG_MCR(0x8828) 200ecabb5e6SShekhar Chauhan #define L3CMPCTRL REG_BIT(23) 20102c4e64aSShekhar Chauhan #define ENCOMPPERFFIX REG_BIT(18) 20202c4e64aSShekhar Chauhan 203aaa536a8SMatt Roper /* Fuse readout registers for GT */ 204aaa536a8SMatt Roper #define XEHP_FUSE4 XE_REG(0x9114) 205ddb5badeSNirmoy Das #define CFEG_WMTP_DISABLE REG_BIT(20) 206aaa536a8SMatt Roper #define CCS_EN_MASK REG_GENMASK(19, 16) 207aaa536a8SMatt Roper #define GT_L3_EXC_MASK REG_GENMASK(6, 4) 208aaa536a8SMatt Roper 2093512a78aSLucas De Marchi #define MIRROR_FUSE3 XE_REG(0x9118) 2105c82000fSMatt Roper #define XE2_NODE_ENABLE_MASK REG_GENMASK(31, 16) 211d9b79ad2SLucas De Marchi #define L3BANK_PAIR_COUNT 4 2125f36d1ceSFrancois Dugast #define XEHPC_GT_L3_MODE_MASK REG_GENMASK(7, 4) 2135f36d1ceSFrancois Dugast #define XE2_GT_L3_MODE_MASK REG_GENMASK(7, 4) 2145f230a14SLucas De Marchi #define L3BANK_MASK REG_GENMASK(3, 0) 2155f36d1ceSFrancois Dugast #define XELP_GT_L3_MODE_MASK REG_GENMASK(7, 0) 216226bfec8SLucas De Marchi /* on Xe_HP the same fuses indicates mslices instead of L3 banks */ 217d9b79ad2SLucas De Marchi #define MAX_MSLICES 4 2185f230a14SLucas De Marchi #define MEML3_EN_MASK REG_GENMASK(3, 0) 219226bfec8SLucas De Marchi 220dec79386SMichal Wajdeczko #define MIRROR_FUSE1 XE_REG(0x911c) 221dec79386SMichal Wajdeczko 222aaa536a8SMatt Roper #define XELP_EU_ENABLE XE_REG(0x9134) /* "_DISABLE" on Xe_LP */ 223aaa536a8SMatt Roper #define XELP_EU_MASK REG_GENMASK(7, 0) 224dec79386SMichal Wajdeczko #define XELP_GT_SLICE_ENABLE XE_REG(0x9138) 225aaa536a8SMatt Roper #define XELP_GT_GEOMETRY_DSS_ENABLE XE_REG(0x913c) 226226bfec8SLucas De Marchi 2273512a78aSLucas De Marchi #define GT_VEBOX_VDBOX_DISABLE XE_REG(0x9140) 2285f230a14SLucas De Marchi #define GT_VEBOX_DISABLE_MASK REG_GENMASK(19, 16) 2295f230a14SLucas De Marchi #define GT_VDBOX_DISABLE_MASK REG_GENMASK(7, 0) 230226bfec8SLucas De Marchi 2313512a78aSLucas De Marchi #define XEHP_GT_COMPUTE_DSS_ENABLE XE_REG(0x9144) 2323512a78aSLucas De Marchi #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT XE_REG(0x9148) 233015906ffSMatt Roper #define XE2_GT_COMPUTE_DSS_2 XE_REG(0x914c) 234015906ffSMatt Roper #define XE2_GT_GEOMETRY_DSS_1 XE_REG(0x9150) 235015906ffSMatt Roper #define XE2_GT_GEOMETRY_DSS_2 XE_REG(0x9154) 2368cb49012SLucas De Marchi 2373512a78aSLucas De Marchi #define GDRST XE_REG(0x941c) 238d9b79ad2SLucas De Marchi #define GRDOM_GUC REG_BIT(3) 239d9b79ad2SLucas De Marchi #define GRDOM_FULL REG_BIT(0) 240226bfec8SLucas De Marchi 2413512a78aSLucas De Marchi #define MISCCPCTL XE_REG(0x9424) 242d9b79ad2SLucas De Marchi #define DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) 243226bfec8SLucas De Marchi 2443512a78aSLucas De Marchi #define UNSLCGCTL9430 XE_REG(0x9430) 245226bfec8SLucas De Marchi #define MSQDUNIT_CLKGATE_DIS REG_BIT(3) 246226bfec8SLucas De Marchi 2473512a78aSLucas De Marchi #define UNSLICE_UNIT_LEVEL_CLKGATE XE_REG(0x9434) 248226bfec8SLucas De Marchi #define VFUNIT_CLKGATE_DIS REG_BIT(20) 249226bfec8SLucas De Marchi #define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */ 250226bfec8SLucas De Marchi #define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */ 251226bfec8SLucas De Marchi #define GAMEDIA_CLKGATE_DIS REG_BIT(11) 252226bfec8SLucas De Marchi #define HSUNIT_CLKGATE_DIS REG_BIT(8) 253226bfec8SLucas De Marchi #define VSUNIT_CLKGATE_DIS REG_BIT(3) 254226bfec8SLucas De Marchi 2553512a78aSLucas De Marchi #define UNSLCGCTL9440 XE_REG(0x9440) 256226bfec8SLucas De Marchi #define GAMTLBOACS_CLKGATE_DIS REG_BIT(28) 257226bfec8SLucas De Marchi #define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27) 258226bfec8SLucas De Marchi #define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26) 259226bfec8SLucas De Marchi #define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24) 260226bfec8SLucas De Marchi #define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23) 261226bfec8SLucas De Marchi #define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22) 262226bfec8SLucas De Marchi #define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21) 263226bfec8SLucas De Marchi #define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17) 264226bfec8SLucas De Marchi #define GAMTLBKCR_CLKGATE_DIS REG_BIT(16) 265226bfec8SLucas De Marchi #define GAMTLBGUC_CLKGATE_DIS REG_BIT(15) 266226bfec8SLucas De Marchi #define GAMTLBBLT_CLKGATE_DIS REG_BIT(14) 267226bfec8SLucas De Marchi #define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6) 268226bfec8SLucas De Marchi 2693512a78aSLucas De Marchi #define UNSLCGCTL9444 XE_REG(0x9444) 270226bfec8SLucas De Marchi #define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30) 271226bfec8SLucas De Marchi #define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29) 272226bfec8SLucas De Marchi #define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28) 273226bfec8SLucas De Marchi #define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27) 274226bfec8SLucas De Marchi #define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26) 275226bfec8SLucas De Marchi #define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25) 276226bfec8SLucas De Marchi #define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24) 277226bfec8SLucas De Marchi #define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23) 278226bfec8SLucas De Marchi #define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22) 279226bfec8SLucas De Marchi #define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21) 280226bfec8SLucas De Marchi #define GAMTLBMERT_CLKGATE_DIS REG_BIT(20) 281226bfec8SLucas De Marchi #define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19) 282226bfec8SLucas De Marchi #define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18) 283226bfec8SLucas De Marchi #define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17) 284226bfec8SLucas De Marchi #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16) 285226bfec8SLucas De Marchi #define LTCDD_CLKGATE_DIS REG_BIT(10) 286226bfec8SLucas De Marchi 2873512a78aSLucas De Marchi #define XEHP_SLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x94d4) 288226bfec8SLucas De Marchi #define L3_CR2X_CLKGATE_DIS REG_BIT(17) 2895f230a14SLucas De Marchi #define L3_CLKGATE_DIS REG_BIT(16) 2905f230a14SLucas De Marchi #define NODEDSS_CLKGATE_DIS REG_BIT(12) 2915f230a14SLucas De Marchi #define MSCUNIT_CLKGATE_DIS REG_BIT(10) 2925f230a14SLucas De Marchi #define RCCUNIT_CLKGATE_DIS REG_BIT(7) 2935f230a14SLucas De Marchi #define SARBUNIT_CLKGATE_DIS REG_BIT(5) 294bad3644dSDnyaneshwar Bhadane #define SBEUNIT_CLKGATE_DIS REG_BIT(4) 295226bfec8SLucas De Marchi 2963512a78aSLucas De Marchi #define UNSLICE_UNIT_LEVEL_CLKGATE2 XE_REG(0x94e4) 297d9b79ad2SLucas De Marchi #define VSUNIT_CLKGATE2_DIS REG_BIT(19) 298226bfec8SLucas De Marchi 2993512a78aSLucas De Marchi #define SUBSLICE_UNIT_LEVEL_CLKGATE XE_REG_MCR(0x9524) 300226bfec8SLucas De Marchi #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28) 301226bfec8SLucas De Marchi #define GWUNIT_CLKGATE_DIS REG_BIT(16) 302226bfec8SLucas De Marchi 3033512a78aSLucas De Marchi #define SUBSLICE_UNIT_LEVEL_CLKGATE2 XE_REG_MCR(0x9528) 304226bfec8SLucas De Marchi #define CPSSUNIT_CLKGATE_DIS REG_BIT(9) 305226bfec8SLucas De Marchi 3063512a78aSLucas De Marchi #define SSMCGCTL9530 XE_REG_MCR(0x9530) 307226bfec8SLucas De Marchi #define RTFUNIT_CLKGATE_DIS REG_BIT(18) 308226bfec8SLucas De Marchi 3093512a78aSLucas De Marchi #define DFR_RATIO_EN_AND_CHICKEN XE_REG_MCR(0x9550) 3105f230a14SLucas De Marchi #define DFR_DISABLE REG_BIT(9) 311226bfec8SLucas De Marchi 3123512a78aSLucas De Marchi #define RPNSWREQ XE_REG(0xa008) 313e12ef392SLucas De Marchi #define REQ_RATIO_MASK REG_GENMASK(31, 23) 31443efd3baSVinay Belgaumkar 31543efd3baSVinay Belgaumkar #define RP_CONTROL XE_REG(0xa024) 31643efd3baSVinay Belgaumkar #define RPSWCTL_MASK REG_GENMASK(10, 9) 31743efd3baSVinay Belgaumkar #define RPSWCTL_ENABLE REG_FIELD_PREP(RPSWCTL_MASK, 2) 31843efd3baSVinay Belgaumkar #define RPSWCTL_DISABLE REG_FIELD_PREP(RPSWCTL_MASK, 0) 3193512a78aSLucas De Marchi #define RC_CONTROL XE_REG(0xa090) 320975e4a37SVinay Belgaumkar #define RC_CTL_HW_ENABLE REG_BIT(31) 321975e4a37SVinay Belgaumkar #define RC_CTL_TO_MODE REG_BIT(28) 322975e4a37SVinay Belgaumkar #define RC_CTL_RC6_ENABLE REG_BIT(18) 3233512a78aSLucas De Marchi #define RC_STATE XE_REG(0xa094) 324975e4a37SVinay Belgaumkar #define RC_IDLE_HYSTERSIS XE_REG(0xa0ac) 32538e8c418SRiana Tauro #define MEDIA_POWERGATE_IDLE_HYSTERESIS XE_REG(0xa0c4) 32638e8c418SRiana Tauro #define RENDER_POWERGATE_IDLE_HYSTERESIS XE_REG(0xa0c8) 327226bfec8SLucas De Marchi 3283512a78aSLucas De Marchi #define PMINTRMSK XE_REG(0xa168) 3295f230a14SLucas De Marchi #define PMINTR_DISABLE_REDIRECT_TO_GUC REG_BIT(31) 3305f230a14SLucas De Marchi #define ARAT_EXPIRED_INTRMSK REG_BIT(9) 331226bfec8SLucas De Marchi 3323512a78aSLucas De Marchi #define FORCEWAKE_GT XE_REG(0xa188) 333226bfec8SLucas De Marchi 3349276bcc2SRiana Tauro #define POWERGATE_ENABLE XE_REG(0xa210) 33538e8c418SRiana Tauro #define RENDER_POWERGATE_ENABLE REG_BIT(0) 33638e8c418SRiana Tauro #define MEDIA_POWERGATE_ENABLE REG_BIT(1) 3379276bcc2SRiana Tauro #define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n)) 3389276bcc2SRiana Tauro #define VDN_MFXVDENC_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n)) 339226bfec8SLucas De Marchi 3403512a78aSLucas De Marchi #define CTC_MODE XE_REG(0xa26c) 3415f230a14SLucas De Marchi #define CTC_SHIFT_PARAMETER_MASK REG_GENMASK(2, 1) 3425f230a14SLucas De Marchi #define CTC_SOURCE_DIVIDE_LOGIC REG_BIT(0) 343226bfec8SLucas De Marchi 3443512a78aSLucas De Marchi #define FORCEWAKE_RENDER XE_REG(0xa278) 3453512a78aSLucas De Marchi #define FORCEWAKE_MEDIA_VDBOX(n) XE_REG(0xa540 + (n) * 4) 3463512a78aSLucas De Marchi #define FORCEWAKE_MEDIA_VEBOX(n) XE_REG(0xa560 + (n) * 4) 347f4c33ae8SDaniele Ceraolo Spurio #define FORCEWAKE_GSC XE_REG(0xa618) 348226bfec8SLucas De Marchi 349ca2acce7SLucas De Marchi #define XEHPC_LNCFMISCCFGREG0 XE_REG_MCR(0xb01c, XE_REG_OPTION_MASKED) 350a19220faSLucas De Marchi #define XEHPC_OVRLSCCC REG_BIT(0) 351a19220faSLucas De Marchi 352aaa536a8SMatt Roper /* L3 Cache Control */ 3539fbd0adbSJanga Rahul Kumar #define LNCFCMOCS_REG_COUNT 32 354aaa536a8SMatt Roper #define XELP_LNCFCMOCS(i) XE_REG(0xb020 + (i) * 4) 355aaa536a8SMatt Roper #define XEHP_LNCFCMOCS(i) XE_REG_MCR(0xb020 + (i) * 4) 3569fbd0adbSJanga Rahul Kumar #define L3_UPPER_LKUP_MASK REG_BIT(23) 3579fbd0adbSJanga Rahul Kumar #define L3_UPPER_GLBGO_MASK REG_BIT(22) 3589fbd0adbSJanga Rahul Kumar #define L3_UPPER_IDX_CACHEABILITY_MASK REG_GENMASK(21, 20) 3599fbd0adbSJanga Rahul Kumar #define L3_UPPER_IDX_SCC_MASK REG_GENMASK(19, 17) 3609fbd0adbSJanga Rahul Kumar #define L3_UPPER_IDX_ESC_MASK REG_BIT(16) 3619fbd0adbSJanga Rahul Kumar #define L3_LKUP_MASK REG_BIT(7) 3629fbd0adbSJanga Rahul Kumar #define L3_LKUP(value) REG_FIELD_PREP(L3_LKUP_MASK, value) 3639fbd0adbSJanga Rahul Kumar #define L3_GLBGO_MASK REG_BIT(6) 3649fbd0adbSJanga Rahul Kumar #define L3_GLBGO(value) REG_FIELD_PREP(L3_GLBGO_MASK, value) 3659fbd0adbSJanga Rahul Kumar #define L3_CACHEABILITY_MASK REG_GENMASK(5, 4) 3669fbd0adbSJanga Rahul Kumar #define L3_CACHEABILITY(value) REG_FIELD_PREP(L3_CACHEABILITY_MASK, value) 3679fbd0adbSJanga Rahul Kumar #define L3_SCC_MASK REG_GENMASK(3, 1) 3689fbd0adbSJanga Rahul Kumar #define L3_SCC(value) REG_FIELD_PREP(L3_SCC_MASK, value) 3699fbd0adbSJanga Rahul Kumar #define L3_ESC_MASK REG_BIT(0) 3709fbd0adbSJanga Rahul Kumar #define L3_ESC(value) REG_FIELD_PREP(L3_ESC_MASK, value) 371aaa536a8SMatt Roper 3723512a78aSLucas De Marchi #define XEHP_L3NODEARBCFG XE_REG_MCR(0xb0b4) 373911aeb0fSLucas De Marchi #define XEHP_LNESPARE REG_BIT(19) 374911aeb0fSLucas De Marchi 3752009e808SAkshata Jahagirdar #define L3SQCREG2 XE_REG_MCR(0xb104) 3762009e808SAkshata Jahagirdar #define COMPMEMRD256BOVRFETCHEN REG_BIT(20) 3772009e808SAkshata Jahagirdar 37802c4e64aSShekhar Chauhan #define L3SQCREG3 XE_REG_MCR(0xb108) 37902c4e64aSShekhar Chauhan #define COMPPWOVERFETCHEN REG_BIT(28) 38002c4e64aSShekhar Chauhan 3813512a78aSLucas De Marchi #define XEHP_L3SQCREG5 XE_REG_MCR(0xb158) 38211f78b13SLucas De Marchi #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) 38311f78b13SLucas De Marchi 3843512a78aSLucas De Marchi #define XEHP_L3SCQREG7 XE_REG_MCR(0xb188) 385911aeb0fSLucas De Marchi #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3) 386911aeb0fSLucas De Marchi 387bad3644dSDnyaneshwar Bhadane #define XEHPC_L3CLOS_MASK(i) XE_REG_MCR(0xb194 + (i) * 8) 388bad3644dSDnyaneshwar Bhadane 38901570b44SMatthew Auld #define XE2_GLOBAL_INVAL XE_REG(0xb404) 39001570b44SMatthew Auld 39101570b44SMatthew Auld #define SCRATCH1LPFC XE_REG(0xb474) 39201570b44SMatthew Auld #define EN_L3_RW_CCS_CACHE_FLUSH REG_BIT(0) 39301570b44SMatthew Auld 394f6c39feeSShekhar Chauhan #define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658) 395f6c39feeSShekhar Chauhan 396c01c6066SNirmoy Das #define XE2_TDF_CTRL XE_REG(0xb418) 397c01c6066SNirmoy Das #define TRANSIENT_FLUSH_REQUEST REG_BIT(0) 398c01c6066SNirmoy Das 3993512a78aSLucas De Marchi #define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28) 4003512a78aSLucas De Marchi #define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c) 4013512a78aSLucas De Marchi #define COMP_MOD_CTRL XE_REG_MCR(0xcf30) 4023512a78aSLucas De Marchi #define XEHP_VDBX_MOD_CTRL XE_REG_MCR(0xcf34) 403ff063430SMatt Roper #define XELPMP_VDBX_MOD_CTRL XE_REG(0xcf34) 4043512a78aSLucas De Marchi #define XEHP_VEBX_MOD_CTRL XE_REG_MCR(0xcf38) 405ff063430SMatt Roper #define XELPMP_VEBX_MOD_CTRL XE_REG(0xcf38) 406a19220faSLucas De Marchi #define FORCE_MISS_FTLB REG_BIT(3) 407a19220faSLucas De Marchi 4083512a78aSLucas De Marchi #define XEHP_GAMSTLB_CTRL XE_REG_MCR(0xcf4c) 409911aeb0fSLucas De Marchi #define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12) 410911aeb0fSLucas De Marchi #define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11) 411911aeb0fSLucas De Marchi #define TAG_BLOCK_CLKGATE_DIS REG_BIT(7) 412911aeb0fSLucas De Marchi 4133512a78aSLucas De Marchi #define XEHP_GAMCNTRL_CTRL XE_REG_MCR(0xcf54) 414911aeb0fSLucas De Marchi #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12) 415911aeb0fSLucas De Marchi #define GLOBAL_INVALIDATION_MODE REG_BIT(2) 416911aeb0fSLucas De Marchi 417466a6c38SMichal Wajdeczko #define LMEM_CFG XE_REG(0xcf58) 418466a6c38SMichal Wajdeczko #define LMEM_EN REG_BIT(31) 419466a6c38SMichal Wajdeczko #define LMTT_DIR_PTR REG_GENMASK(30, 0) /* in multiples of 64KB */ 420466a6c38SMichal Wajdeczko 421bad3644dSDnyaneshwar Bhadane #define HALF_SLICE_CHICKEN5 XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED) 422bad3644dSDnyaneshwar Bhadane #define DISABLE_SAMPLE_G_PERFORMANCE REG_BIT(0) 423bad3644dSDnyaneshwar Bhadane 424c8d4524eSJosé Roberto de Souza #define SAMPLER_INSTDONE XE_REG_MCR(0xe160) 425c8d4524eSJosé Roberto de Souza #define ROW_INSTDONE XE_REG_MCR(0xe164) 426c8d4524eSJosé Roberto de Souza 427ca2acce7SLucas De Marchi #define SAMPLER_MODE XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED) 428226bfec8SLucas De Marchi #define ENABLE_SMALLPL REG_BIT(15) 429226bfec8SLucas De Marchi #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) 430d9b79ad2SLucas De Marchi #define SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) 431f8ebadd0SMatt Atwood #define INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0) 432226bfec8SLucas De Marchi 433ca2acce7SLucas De Marchi #define HALF_SLICE_CHICKEN7 XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED) 4344d5ab121SLucas De Marchi #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) 435598dc939SBommu Krishnaiah #define CLEAR_OPTIMIZATION_DISABLE REG_BIT(6) 4364d5ab121SLucas De Marchi 437ca2acce7SLucas De Marchi #define CACHE_MODE_SS XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED) 4384688d9ceSLucas De Marchi #define DISABLE_ECC REG_BIT(5) 4394d5ab121SLucas De Marchi #define ENABLE_PREFETCH_INTO_IC REG_BIT(3) 4404688d9ceSLucas De Marchi 441ca2acce7SLucas De Marchi #define ROW_CHICKEN4 XE_REG_MCR(0xe48c, XE_REG_OPTION_MASKED) 442d9b79ad2SLucas De Marchi #define DISABLE_GRF_CLEAR REG_BIT(13) 443226bfec8SLucas De Marchi #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11) 444d9b79ad2SLucas De Marchi #define DISABLE_TDL_PUSH REG_BIT(9) 445d9b79ad2SLucas De Marchi #define DIS_PICK_2ND_EU REG_BIT(7) 446d9b79ad2SLucas De Marchi #define DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4) 447226bfec8SLucas De Marchi #define THREAD_EX_ARB_MODE REG_GENMASK(3, 2) 448226bfec8SLucas De Marchi #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) 449226bfec8SLucas De Marchi 450ff063430SMatt Roper #define ROW_CHICKEN3 XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED) 4517f3ee7d8SHaridhar Kalvala #define XE2_EUPEND_CHK_FLUSH_DIS REG_BIT(14) 452ff063430SMatt Roper #define DIS_FIX_EOT1_FLUSH REG_BIT(9) 453ff063430SMatt Roper 4549fbedddfSShekhar Chauhan #define TDL_TSL_CHICKEN XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED) 45521ff3a16STejas Upadhyay #define STK_ID_RESTRICT REG_BIT(12) 4569fbedddfSShekhar Chauhan #define SLM_WMTP_RESTORE REG_BIT(11) 4579fbedddfSShekhar Chauhan 458ca2acce7SLucas De Marchi #define ROW_CHICKEN XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED) 4594d5ab121SLucas De Marchi #define UGM_BACKUP_MODE REG_BIT(13) 4604d5ab121SLucas De Marchi #define MDQ_ARBITRATION_MODE REG_BIT(12) 4611db9a9dcSAshutosh Dixit #define STALL_DOP_GATING_DISABLE REG_BIT(5) 462bad3644dSDnyaneshwar Bhadane #define EARLY_EOT_DIS REG_BIT(1) 4634d5ab121SLucas De Marchi 464ca2acce7SLucas De Marchi #define ROW_CHICKEN2 XE_REG_MCR(0xe4f4, XE_REG_OPTION_MASKED) 465d9b79ad2SLucas De Marchi #define DISABLE_READ_SUPPRESSION REG_BIT(15) 466d9b79ad2SLucas De Marchi #define DISABLE_EARLY_READ REG_BIT(14) 467d9b79ad2SLucas De Marchi #define ENABLE_LARGE_GRF_MODE REG_BIT(12) 468d9b79ad2SLucas De Marchi #define PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) 4690267ee19SRadhakrishna Sripada #define DISABLE_TDL_SVHS_GATING REG_BIT(1) 470d9b79ad2SLucas De Marchi #define DISABLE_DOP_GATING REG_BIT(0) 471226bfec8SLucas De Marchi 472aaa536a8SMatt Roper #define RT_CTRL XE_REG_MCR(0xe530) 473aaa536a8SMatt Roper #define DIS_NULL_QUERY REG_BIT(10) 474aaa536a8SMatt Roper 475d62753a5SDaniele Ceraolo Spurio #define EU_SYSTOLIC_LIC_THROTTLE_CTL_WITH_LOCK XE_REG_MCR(0xe534) 476d62753a5SDaniele Ceraolo Spurio #define EU_SYSTOLIC_LIC_THROTTLE_CTL_LOCK_BIT REG_BIT(31) 477d62753a5SDaniele Ceraolo Spurio 478ca2acce7SLucas De Marchi #define XEHP_HDC_CHICKEN0 XE_REG_MCR(0xe5f0, XE_REG_OPTION_MASKED) 4794d5ab121SLucas De Marchi #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) 480c7e4a611SMatt Roper #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3) 4814d5ab121SLucas De Marchi 4823512a78aSLucas De Marchi #define LSC_CHICKEN_BIT_0 XE_REG_MCR(0xe7c8) 4834688d9ceSLucas De Marchi #define DISABLE_D8_D16_COASLESCE REG_BIT(30) 4847f3ee7d8SHaridhar Kalvala #define WR_REQ_CHAINING_DIS REG_BIT(26) 485bad3644dSDnyaneshwar Bhadane #define TGM_WRITE_EOM_FORCE REG_BIT(17) 4864d5ab121SLucas De Marchi #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) 487bad3644dSDnyaneshwar Bhadane #define SEQUENTIAL_ACCESS_UPGRADE_DISABLE REG_BIT(13) 4884d5ab121SLucas De Marchi 4893512a78aSLucas De Marchi #define LSC_CHICKEN_BIT_0_UDW XE_REG_MCR(0xe7c8 + 4) 4905fdd4b21SShekhar Chauhan #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32) 4914d5ab121SLucas De Marchi #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) 492bad3644dSDnyaneshwar Bhadane #define XE2_ALLOC_DPA_STARVE_FIX_DIS REG_BIT(47 - 32) 493bad3644dSDnyaneshwar Bhadane #define ENABLE_SMP_LD_RENDER_SURFACE_CONTROL REG_BIT(44 - 32) 4944d5ab121SLucas De Marchi #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) 4954d5ab121SLucas De Marchi #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) 4964d5ab121SLucas De Marchi #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32) 4974d5ab121SLucas De Marchi #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) 4984688d9ceSLucas De Marchi 4993512a78aSLucas De Marchi #define SARB_CHICKEN1 XE_REG_MCR(0xe90c) 500226bfec8SLucas De Marchi #define COMP_CKN_IN REG_GENMASK(30, 29) 501226bfec8SLucas De Marchi 50298ce59e9SLucas De Marchi #define RCU_MODE XE_REG(0x14800, XE_REG_OPTION_MASKED) 5030d97ecceSNiranjana Vishwanathapura #define RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1) 504d9b79ad2SLucas De Marchi #define RCU_MODE_CCS_ENABLE REG_BIT(0) 505226bfec8SLucas De Marchi 5060d97ecceSNiranjana Vishwanathapura /* 5070d97ecceSNiranjana Vishwanathapura * Total of 4 cslices, where each cslice is in the form: 5080d97ecceSNiranjana Vishwanathapura * [0-3] CCS ID 5090d97ecceSNiranjana Vishwanathapura * [4-6] RSVD 5100d97ecceSNiranjana Vishwanathapura * [7] Disabled 5110d97ecceSNiranjana Vishwanathapura */ 5120d97ecceSNiranjana Vishwanathapura #define CCS_MODE XE_REG(0x14804) 5130d97ecceSNiranjana Vishwanathapura #define CCS_MODE_CSLICE_0_3_MASK REG_GENMASK(11, 0) /* 3 bits per cslice */ 5140d97ecceSNiranjana Vishwanathapura #define CCS_MODE_CSLICE_MASK 0x7 /* CCS0-3 + rsvd */ 5150d97ecceSNiranjana Vishwanathapura #define CCS_MODE_CSLICE_WIDTH ilog2(CCS_MODE_CSLICE_MASK + 1) 5160d97ecceSNiranjana Vishwanathapura #define CCS_MODE_CSLICE(cslice, ccs) \ 5170d97ecceSNiranjana Vishwanathapura ((ccs) << ((cslice) * CCS_MODE_CSLICE_WIDTH)) 5180d97ecceSNiranjana Vishwanathapura 5193512a78aSLucas De Marchi #define FORCEWAKE_ACK_GT XE_REG(0x130044) 5207ecea18eSHimal Prasad Ghimiray 5217ecea18eSHimal Prasad Ghimiray /* Applicable for all FORCEWAKE_DOMAIN and FORCEWAKE_ACK_DOMAIN regs */ 5227ecea18eSHimal Prasad Ghimiray #define FORCEWAKE_KERNEL 0 5237ecea18eSHimal Prasad Ghimiray #define FORCEWAKE_MT(bit) BIT(bit) 5247ecea18eSHimal Prasad Ghimiray #define FORCEWAKE_MT_MASK(bit) BIT((bit) + 16) 525226bfec8SLucas De Marchi 526aaa536a8SMatt Roper #define MTL_MEDIA_PERF_LIMIT_REASONS XE_REG(0x138030) 5277b076d14SBadal Nilawar #define MTL_MEDIA_MC6 XE_REG(0x138048) 5287b076d14SBadal Nilawar 5293512a78aSLucas De Marchi #define GT_CORE_STATUS XE_REG(0x138060) 530e12ef392SLucas De Marchi #define RCN_MASK REG_GENMASK(2, 0) 5317b076d14SBadal Nilawar #define GT_C0 0 5327b076d14SBadal Nilawar #define GT_C6 3 533226bfec8SLucas De Marchi 5343512a78aSLucas De Marchi #define GT_GFX_RC6_LOCKED XE_REG(0x138104) 5353512a78aSLucas De Marchi #define GT_GFX_RC6 XE_REG(0x138108) 536226bfec8SLucas De Marchi 537aaa536a8SMatt Roper #define GT0_PERF_LIMIT_REASONS XE_REG(0x1381a8) 538aaa536a8SMatt Roper #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 539aaa536a8SMatt Roper #define PROCHOT_MASK REG_BIT(0) 540aaa536a8SMatt Roper #define THERMAL_LIMIT_MASK REG_BIT(1) 541aaa536a8SMatt Roper #define RATL_MASK REG_BIT(5) 542aaa536a8SMatt Roper #define VR_THERMALERT_MASK REG_BIT(6) 543aaa536a8SMatt Roper #define VR_TDC_MASK REG_BIT(7) 544aaa536a8SMatt Roper #define POWER_LIMIT_4_MASK REG_BIT(8) 545aaa536a8SMatt Roper #define POWER_LIMIT_1_MASK REG_BIT(10) 546aaa536a8SMatt Roper #define POWER_LIMIT_2_MASK REG_BIT(11) 547aaa536a8SMatt Roper 548fbcdc9d3SBadal Nilawar #define GT_PERF_STATUS XE_REG(0x1381b4) 549fbcdc9d3SBadal Nilawar #define VOLTAGE_MASK REG_GENMASK(10, 0) 550fbcdc9d3SBadal Nilawar 55142b266beSMichal Wajdeczko /* 55242b266beSMichal Wajdeczko * Note: Interrupt registers 1900xx are VF accessible only until version 12.50. 55342b266beSMichal Wajdeczko * On newer platforms, VFs are using memory-based interrupts instead. 55442b266beSMichal Wajdeczko * However, for simplicity we keep this XE_REG_OPTION_VF tag intact. 55542b266beSMichal Wajdeczko */ 55642b266beSMichal Wajdeczko 55742b266beSMichal Wajdeczko #define GT_INTR_DW(x) XE_REG(0x190018 + ((x) * 4), XE_REG_OPTION_VF) 5587158a688SMichal Wajdeczko #define INTR_GSC REG_BIT(31) 5597158a688SMichal Wajdeczko #define INTR_GUC REG_BIT(25) 5607158a688SMichal Wajdeczko #define INTR_MGUC REG_BIT(24) 5617158a688SMichal Wajdeczko #define INTR_BCS8 REG_BIT(23) 5627158a688SMichal Wajdeczko #define INTR_BCS(x) REG_BIT(15 - (x)) 5637158a688SMichal Wajdeczko #define INTR_CCS(x) REG_BIT(4 + (x)) 5647158a688SMichal Wajdeczko #define INTR_RCS0 REG_BIT(0) 5657158a688SMichal Wajdeczko #define INTR_VECS(x) REG_BIT(31 - (x)) 5667158a688SMichal Wajdeczko #define INTR_VCS(x) REG_BIT(x) 567226bfec8SLucas De Marchi 56842b266beSMichal Wajdeczko #define RENDER_COPY_INTR_ENABLE XE_REG(0x190030, XE_REG_OPTION_VF) 56942b266beSMichal Wajdeczko #define VCS_VECS_INTR_ENABLE XE_REG(0x190034, XE_REG_OPTION_VF) 57042b266beSMichal Wajdeczko #define GUC_SG_INTR_ENABLE XE_REG(0x190038, XE_REG_OPTION_VF) 571226bfec8SLucas De Marchi #define ENGINE1_MASK REG_GENMASK(31, 16) 572226bfec8SLucas De Marchi #define ENGINE0_MASK REG_GENMASK(15, 0) 57342b266beSMichal Wajdeczko #define GPM_WGBOXPERF_INTR_ENABLE XE_REG(0x19003c, XE_REG_OPTION_VF) 57442b266beSMichal Wajdeczko #define GUNIT_GSC_INTR_ENABLE XE_REG(0x190044, XE_REG_OPTION_VF) 57542b266beSMichal Wajdeczko #define CCS_RSVD_INTR_ENABLE XE_REG(0x190048, XE_REG_OPTION_VF) 576226bfec8SLucas De Marchi 57742b266beSMichal Wajdeczko #define INTR_IDENTITY_REG(x) XE_REG(0x190060 + ((x) * 4), XE_REG_OPTION_VF) 5786b7ece97SMatt Roper #define INTR_DATA_VALID REG_BIT(31) 5796b7ece97SMatt Roper #define INTR_ENGINE_INSTANCE(x) REG_FIELD_GET(GENMASK(25, 20), x) 5806b7ece97SMatt Roper #define INTR_ENGINE_CLASS(x) REG_FIELD_GET(GENMASK(18, 16), x) 5816b7ece97SMatt Roper #define INTR_ENGINE_INTR(x) REG_FIELD_GET(GENMASK(15, 0), x) 582226bfec8SLucas De Marchi #define OTHER_GUC_INSTANCE 0 583eb08104fSDaniele Ceraolo Spurio #define OTHER_GSC_HECI2_INSTANCE 3 58429654910SDaniele Ceraolo Spurio #define OTHER_GSC_INSTANCE 6 585226bfec8SLucas De Marchi 58642b266beSMichal Wajdeczko #define IIR_REG_SELECTOR(x) XE_REG(0x190070 + ((x) * 4), XE_REG_OPTION_VF) 58742b266beSMichal Wajdeczko #define RCS0_RSVD_INTR_MASK XE_REG(0x190090, XE_REG_OPTION_VF) 58842b266beSMichal Wajdeczko #define BCS_RSVD_INTR_MASK XE_REG(0x1900a0, XE_REG_OPTION_VF) 58942b266beSMichal Wajdeczko #define VCS0_VCS1_INTR_MASK XE_REG(0x1900a8, XE_REG_OPTION_VF) 59042b266beSMichal Wajdeczko #define VCS2_VCS3_INTR_MASK XE_REG(0x1900ac, XE_REG_OPTION_VF) 59142b266beSMichal Wajdeczko #define VECS0_VECS1_INTR_MASK XE_REG(0x1900d0, XE_REG_OPTION_VF) 592eb08104fSDaniele Ceraolo Spurio #define HECI2_RSVD_INTR_MASK XE_REG(0x1900e4) 59342b266beSMichal Wajdeczko #define GUC_SG_INTR_MASK XE_REG(0x1900e8, XE_REG_OPTION_VF) 59442b266beSMichal Wajdeczko #define GPM_WGBOXPERF_INTR_MASK XE_REG(0x1900ec, XE_REG_OPTION_VF) 59542b266beSMichal Wajdeczko #define GUNIT_GSC_INTR_MASK XE_REG(0x1900f4, XE_REG_OPTION_VF) 5963512a78aSLucas De Marchi #define CCS0_CCS1_INTR_MASK XE_REG(0x190100) 5973512a78aSLucas De Marchi #define CCS2_CCS3_INTR_MASK XE_REG(0x190104) 5983512a78aSLucas De Marchi #define XEHPC_BCS1_BCS2_INTR_MASK XE_REG(0x190110) 5993512a78aSLucas De Marchi #define XEHPC_BCS3_BCS4_INTR_MASK XE_REG(0x190114) 6003512a78aSLucas De Marchi #define XEHPC_BCS5_BCS6_INTR_MASK XE_REG(0x190118) 6013512a78aSLucas De Marchi #define XEHPC_BCS7_BCS8_INTR_MASK XE_REG(0x19011c) 60293536c2bSMatt Roper #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11) 60393536c2bSMatt Roper #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8) 604cc244ce5SDaniele Ceraolo Spurio #define GSC_ER_COMPLETE REG_BIT(5) 60593536c2bSMatt Roper #define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT REG_BIT(4) 60693536c2bSMatt Roper #define GT_CS_MASTER_ERROR_INTERRUPT REG_BIT(3) 60793536c2bSMatt Roper #define GT_RENDER_USER_INTERRUPT REG_BIT(0) 608226bfec8SLucas De Marchi 609226bfec8SLucas De Marchi #endif 610