12ef6d3bfSMatt Roper /* SPDX-License-Identifier: MIT */ 22ef6d3bfSMatt Roper /* 32ef6d3bfSMatt Roper * Copyright © 2022 Intel Corporation 42ef6d3bfSMatt Roper */ 52ef6d3bfSMatt Roper 62ef6d3bfSMatt Roper #ifndef __INTEL_PERF_OA_REGS__ 72ef6d3bfSMatt Roper #define __INTEL_PERF_OA_REGS__ 82ef6d3bfSMatt Roper 92ef6d3bfSMatt Roper #include "i915_reg_defs.h" 102ef6d3bfSMatt Roper 112ef6d3bfSMatt Roper #define GEN7_OACONTROL _MMIO(0x2360) 122ef6d3bfSMatt Roper #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000 132ef6d3bfSMatt Roper #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F 142ef6d3bfSMatt Roper #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6 152ef6d3bfSMatt Roper #define GEN7_OACONTROL_TIMER_ENABLE (1 << 5) 162ef6d3bfSMatt Roper #define GEN7_OACONTROL_FORMAT_A13 (0 << 2) 172ef6d3bfSMatt Roper #define GEN7_OACONTROL_FORMAT_A29 (1 << 2) 182ef6d3bfSMatt Roper #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2) 192ef6d3bfSMatt Roper #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2) 202ef6d3bfSMatt Roper #define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2) 212ef6d3bfSMatt Roper #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2) 222ef6d3bfSMatt Roper #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2) 232ef6d3bfSMatt Roper #define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2) 242ef6d3bfSMatt Roper #define GEN7_OACONTROL_FORMAT_SHIFT 2 252ef6d3bfSMatt Roper #define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1) 262ef6d3bfSMatt Roper #define GEN7_OACONTROL_ENABLE (1 << 0) 272ef6d3bfSMatt Roper 282ef6d3bfSMatt Roper #define GEN8_OACTXID _MMIO(0x2364) 292ef6d3bfSMatt Roper 302ef6d3bfSMatt Roper #define GEN8_OA_DEBUG _MMIO(0x2B04) 312ef6d3bfSMatt Roper #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) 322ef6d3bfSMatt Roper #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) 332ef6d3bfSMatt Roper #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) 342ef6d3bfSMatt Roper #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) 352ef6d3bfSMatt Roper 362ef6d3bfSMatt Roper #define GEN8_OACONTROL _MMIO(0x2B00) 372ef6d3bfSMatt Roper #define GEN8_OA_REPORT_FORMAT_A12 (0 << 2) 382ef6d3bfSMatt Roper #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2) 392ef6d3bfSMatt Roper #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2) 402ef6d3bfSMatt Roper #define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2) 412ef6d3bfSMatt Roper #define GEN8_OA_REPORT_FORMAT_SHIFT 2 422ef6d3bfSMatt Roper #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1) 432ef6d3bfSMatt Roper #define GEN8_OA_COUNTER_ENABLE (1 << 0) 442ef6d3bfSMatt Roper 452ef6d3bfSMatt Roper #define GEN8_OACTXCONTROL _MMIO(0x2360) 462ef6d3bfSMatt Roper #define GEN8_OA_TIMER_PERIOD_MASK 0x3F 472ef6d3bfSMatt Roper #define GEN8_OA_TIMER_PERIOD_SHIFT 2 482ef6d3bfSMatt Roper #define GEN8_OA_TIMER_ENABLE (1 << 1) 492ef6d3bfSMatt Roper #define GEN8_OA_COUNTER_RESUME (1 << 0) 502ef6d3bfSMatt Roper 512ef6d3bfSMatt Roper #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */ 522ef6d3bfSMatt Roper #define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3) 532ef6d3bfSMatt Roper #define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2) 542ef6d3bfSMatt Roper #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1) 552ef6d3bfSMatt Roper #define GEN7_OABUFFER_RESUME (1 << 0) 562ef6d3bfSMatt Roper 572ef6d3bfSMatt Roper #define GEN8_OABUFFER_UDW _MMIO(0x23b4) 582ef6d3bfSMatt Roper #define GEN8_OABUFFER _MMIO(0x2b14) 592ef6d3bfSMatt Roper #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ 602ef6d3bfSMatt Roper 612ef6d3bfSMatt Roper #define GEN7_OASTATUS1 _MMIO(0x2364) 622ef6d3bfSMatt Roper #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0 632ef6d3bfSMatt Roper #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2) 642ef6d3bfSMatt Roper #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1) 652ef6d3bfSMatt Roper #define GEN7_OASTATUS1_REPORT_LOST (1 << 0) 662ef6d3bfSMatt Roper 672ef6d3bfSMatt Roper #define GEN7_OASTATUS2 _MMIO(0x2368) 682ef6d3bfSMatt Roper #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0 692ef6d3bfSMatt Roper #define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ 702ef6d3bfSMatt Roper 712ef6d3bfSMatt Roper #define GEN8_OASTATUS _MMIO(0x2b08) 722ef6d3bfSMatt Roper #define GEN8_OASTATUS_TAIL_POINTER_WRAP (1 << 17) 732ef6d3bfSMatt Roper #define GEN8_OASTATUS_HEAD_POINTER_WRAP (1 << 16) 742ef6d3bfSMatt Roper #define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3) 752ef6d3bfSMatt Roper #define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2) 762ef6d3bfSMatt Roper #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1) 772ef6d3bfSMatt Roper #define GEN8_OASTATUS_REPORT_LOST (1 << 0) 782ef6d3bfSMatt Roper 792ef6d3bfSMatt Roper #define GEN8_OAHEADPTR _MMIO(0x2B0C) 802ef6d3bfSMatt Roper #define GEN8_OAHEADPTR_MASK 0xffffffc0 812ef6d3bfSMatt Roper #define GEN8_OATAILPTR _MMIO(0x2B10) 822ef6d3bfSMatt Roper #define GEN8_OATAILPTR_MASK 0xffffffc0 832ef6d3bfSMatt Roper 842ef6d3bfSMatt Roper #define OABUFFER_SIZE_128K (0 << 3) 852ef6d3bfSMatt Roper #define OABUFFER_SIZE_256K (1 << 3) 862ef6d3bfSMatt Roper #define OABUFFER_SIZE_512K (2 << 3) 872ef6d3bfSMatt Roper #define OABUFFER_SIZE_1M (3 << 3) 882ef6d3bfSMatt Roper #define OABUFFER_SIZE_2M (4 << 3) 892ef6d3bfSMatt Roper #define OABUFFER_SIZE_4M (5 << 3) 902ef6d3bfSMatt Roper #define OABUFFER_SIZE_8M (6 << 3) 912ef6d3bfSMatt Roper #define OABUFFER_SIZE_16M (7 << 3) 922ef6d3bfSMatt Roper 932ef6d3bfSMatt Roper #define GEN12_OA_TLB_INV_CR _MMIO(0xceec) 942ef6d3bfSMatt Roper 952ef6d3bfSMatt Roper /* Gen12 OAR unit */ 962ef6d3bfSMatt Roper #define GEN12_OAR_OACONTROL _MMIO(0x2960) 972ef6d3bfSMatt Roper #define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1 982ef6d3bfSMatt Roper #define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0) 992ef6d3bfSMatt Roper 100a5c3a3cbSUmesh Nerlige Ramappa #define GEN12_OACTXCONTROL(base) _MMIO((base) + 0x360) 1012ef6d3bfSMatt Roper #define GEN12_OAR_OASTATUS _MMIO(0x2968) 1022ef6d3bfSMatt Roper 1032ef6d3bfSMatt Roper /* Gen12 OAG unit */ 1042ef6d3bfSMatt Roper #define GEN12_OAG_OAHEADPTR _MMIO(0xdb00) 1052ef6d3bfSMatt Roper #define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0 1062ef6d3bfSMatt Roper #define GEN12_OAG_OATAILPTR _MMIO(0xdb04) 1072ef6d3bfSMatt Roper #define GEN12_OAG_OATAILPTR_MASK 0xffffffc0 1082ef6d3bfSMatt Roper 1092ef6d3bfSMatt Roper #define GEN12_OAG_OABUFFER _MMIO(0xdb08) 1102ef6d3bfSMatt Roper #define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7) 1112ef6d3bfSMatt Roper #define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3) 1122ef6d3bfSMatt Roper #define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */ 1132ef6d3bfSMatt Roper 1142ef6d3bfSMatt Roper #define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28) 1152ef6d3bfSMatt Roper #define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2 1162ef6d3bfSMatt Roper #define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1) 1172ef6d3bfSMatt Roper #define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0) 1182ef6d3bfSMatt Roper 1192ef6d3bfSMatt Roper #define GEN12_OAG_OACONTROL _MMIO(0xdaf4) 1202ef6d3bfSMatt Roper #define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2 1212ef6d3bfSMatt Roper #define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0) 1222ef6d3bfSMatt Roper 1232ef6d3bfSMatt Roper #define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8) 1242ef6d3bfSMatt Roper #define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) 1252ef6d3bfSMatt Roper #define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) 1262ef6d3bfSMatt Roper #define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) 1272ef6d3bfSMatt Roper #define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) 1282ef6d3bfSMatt Roper 1292ef6d3bfSMatt Roper #define GEN12_OAG_OASTATUS _MMIO(0xdafc) 1302ef6d3bfSMatt Roper #define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2) 1312ef6d3bfSMatt Roper #define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1) 1322ef6d3bfSMatt Roper #define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0) 1332ef6d3bfSMatt Roper 1342ef6d3bfSMatt Roper #define GDT_CHICKEN_BITS _MMIO(0x9840) 1352ef6d3bfSMatt Roper #define GT_NOA_ENABLE 0x00000080 1362ef6d3bfSMatt Roper 137*1cc064dcSUmesh Nerlige Ramappa /* Gen12 OAM unit */ 138*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_HEAD_POINTER_OFFSET (0x1a0) 139*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_HEAD_POINTER_MASK 0xffffffc0 140*1cc064dcSUmesh Nerlige Ramappa 141*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_TAIL_POINTER_OFFSET (0x1a4) 142*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_TAIL_POINTER_MASK 0xffffffc0 143*1cc064dcSUmesh Nerlige Ramappa 144*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_BUFFER_OFFSET (0x1a8) 145*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_BUFFER_SIZE_MASK (0x7) 146*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_BUFFER_SIZE_SHIFT (3) 147*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_BUFFER_MEMORY_SELECT REG_BIT(0) /* 0: PPGTT, 1: GGTT */ 148*1cc064dcSUmesh Nerlige Ramappa 149*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_CONTEXT_CONTROL_OFFSET (0x1bc) 150*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_CONTEXT_CONTROL_TIMER_PERIOD_SHIFT 2 151*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_CONTEXT_CONTROL_TIMER_ENABLE REG_BIT(1) 152*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_CONTEXT_CONTROL_COUNTER_RESUME REG_BIT(0) 153*1cc064dcSUmesh Nerlige Ramappa 154*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_CONTROL_OFFSET (0x194) 155*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_CONTROL_COUNTER_FORMAT_SHIFT 1 156*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_CONTROL_COUNTER_ENABLE REG_BIT(0) 157*1cc064dcSUmesh Nerlige Ramappa 158*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_DEBUG_OFFSET (0x198) 159*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_DEBUG_BUFFER_SIZE_SELECT REG_BIT(12) 160*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_DEBUG_INCLUDE_CLK_RATIO REG_BIT(6) 161*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_DEBUG_DISABLE_CLK_RATIO_REPORTS REG_BIT(5) 162*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_DEBUG_DISABLE_GO_1_0_REPORTS REG_BIT(2) 163*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_DEBUG_DISABLE_CTX_SWITCH_REPORTS REG_BIT(1) 164*1cc064dcSUmesh Nerlige Ramappa 165*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_STATUS_OFFSET (0x19c) 166*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_STATUS_COUNTER_OVERFLOW REG_BIT(2) 167*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_STATUS_BUFFER_OVERFLOW REG_BIT(1) 168*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_STATUS_REPORT_LOST REG_BIT(0) 169*1cc064dcSUmesh Nerlige Ramappa 170*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_MMIO_TRG_OFFSET (0x1d0) 171*1cc064dcSUmesh Nerlige Ramappa 172*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_MMIO_TRG(base) \ 173*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_MMIO_TRG_OFFSET) 174*1cc064dcSUmesh Nerlige Ramappa 175*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_HEAD_POINTER(base) \ 176*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_HEAD_POINTER_OFFSET) 177*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_TAIL_POINTER(base) \ 178*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_TAIL_POINTER_OFFSET) 179*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_BUFFER(base) \ 180*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_BUFFER_OFFSET) 181*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_CONTEXT_CONTROL(base) \ 182*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_CONTEXT_CONTROL_OFFSET) 183*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_CONTROL(base) \ 184*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_CONTROL_OFFSET) 185*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_DEBUG(base) \ 186*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_DEBUG_OFFSET) 187*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_STATUS(base) \ 188*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_STATUS_OFFSET) 189*1cc064dcSUmesh Nerlige Ramappa 190*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_CEC0_0_OFFSET (0x40) 191*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_CEC7_1_OFFSET (0x7c) 192*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_CEC0_0(base) \ 193*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_CEC0_0_OFFSET) 194*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_CEC7_1(base) \ 195*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_CEC7_1_OFFSET) 196*1cc064dcSUmesh Nerlige Ramappa 197*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_STARTTRIG1_OFFSET (0x00) 198*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_STARTTRIG8_OFFSET (0x1c) 199*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_STARTTRIG1(base) \ 200*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_STARTTRIG1_OFFSET) 201*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_STARTTRIG8(base) \ 202*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_STARTTRIG8_OFFSET) 203*1cc064dcSUmesh Nerlige Ramappa 204*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_REPORTTRIG1_OFFSET (0x20) 205*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_REPORTTRIG8_OFFSET (0x3c) 206*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_REPORTTRIG1(base) \ 207*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_REPORTTRIG1_OFFSET) 208*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_REPORTTRIG8(base) \ 209*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_REPORTTRIG8_OFFSET) 210*1cc064dcSUmesh Nerlige Ramappa 211*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_PERF_COUNTER_B0_OFFSET (0x84) 212*1cc064dcSUmesh Nerlige Ramappa #define GEN12_OAM_PERF_COUNTER_B(base, idx) \ 213*1cc064dcSUmesh Nerlige Ramappa _MMIO((base) + GEN12_OAM_PERF_COUNTER_B0_OFFSET + 4 * (idx)) 214*1cc064dcSUmesh Nerlige Ramappa 2152ef6d3bfSMatt Roper #endif /* __INTEL_PERF_OA_REGS__ */ 216