/freebsd/sys/contrib/device-tree/src/mips/qca/ |
H A D | ar9331.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include <dt-bindings/clock/ath79-clk.h> 7 #address-cells = <1>; 8 #size-cells = <1>; 11 #address-cells = <1>; 12 #size-cells = <0>; 17 clocks = <&pll ATH79_CLK_CPU>; 22 cpuintc: interrupt-controller { 23 compatible = "qca,ar7100-cpu-intc"; 25 interrupt-controller; [all …]
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/freebsd/sys/contrib/device-tree/Bindings/phy/ |
H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus [all...] |
H A D | nvidia,tegra124-xusb-padctl.txt | 11 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 12 super-speed USB. Other lanes are for various types of low-speed, full-speed 13 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 14 contains a software-configurable mux that sits between the I/O controller 17 In addition to per-lane configuration, USB 3.0 ports may require additional 18 settings on a per-board basis. 20 Pads will be represented as children of the top-level XUSB pad controller 23 PHY bindings, as described by the phy-bindings.txt file in this directory. 34 -------------------- 35 - compatible: Must be: [all …]
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H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or 22 super-speed USB. Other lanes are for various types of low-speed, full-speed 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller 24 contains a software-configurable mux that sits between the I/O controller [all …]
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/freebsd/sys/contrib/device-tree/Bindings/net/ |
H A D | qca,ar71xx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - $ref: ethernet-controller.yaml# 13 - Oleksij Rempel <o.rempel@pengutronix.de> 18 - items: 19 - enum: 20 - qca,ar7100-eth # Atheros AR7100 21 - qca,ar7240-eth # Atheros AR7240 22 - qca,ar7241-eth # Atheros AR7241 [all …]
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H A D | rockchip-dwmac.txt | 6 - compatible: should be "rockchip,<name>-gamc" 7 "rockchip,px30-gmac": found on PX30 SoCs 8 "rockchip,rk3128-gmac": found on RK312x SoCs 9 "rockchip,rk3228-gmac": found on RK322x SoCs 10 "rockchip,rk3288-gmac": found on RK3288 SoCs 11 "rockchip,rk3328-gmac": found on RK3328 SoCs 12 "rockchip,rk3366-gmac": found on RK3366 SoCs 13 "rockchip,rk3368-gmac": found on RK3368 SoCs 14 "rockchip,rk3399-gmac": found on RK3399 SoCs 15 "rockchip,rv1108-gmac": found on RV1108 SoCs [all …]
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/freebsd/sys/contrib/device-tree/Bindings/c6x/ |
H A D | clocks.txt | 1 C6X PLL Clock Controllers 2 ------------------------- 4 This is a first-cut support for the SoC clock controllers. This is still 10 - compatible: "ti,c64x+pll" 11 May also have SoC-specific value to support SoC-specific initialization 13 "ti,c6455-pll" 14 "ti,c6457-pll" 15 "ti,c6472-pll" 16 "ti,c6474-pll" 18 - reg: base address and size of register area [all …]
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/freebsd/sys/contrib/device-tree/Bindings/net/dsa/ |
H A D | ar9331.txt | 1 Atheros AR9331 built-in switch 4 It is a switch built-in to Atheros AR9331 WiSoC and addressable over internal 5 MDIO bus. All PHYs are built-in as well. 9 - compatible: should be: "qca,ar9331-switch" 10 - reg: Address on the MII bus for the switch. 11 - resets : Must contain an entry for each entry in reset-names. 12 - reset-names : Must include the following entries: "switch" 13 - interrupt-parent: Phandle to the parent interrupt controller 14 - interrupts: IRQ line for the switch 15 - interrupt-controller: Indicates the switch is itself an interrupt [all …]
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H A D | qca8k.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schema [all...] |
/freebsd/sys/contrib/device-tree/Bindings/sound/ |
H A D | adi,adau1701.txt | 5 - compatible: Should contain "adi,adau1701" 6 - reg: The i2c address. Value depends on the state of ADDR0 11 - reset-gpio: A GPIO spec to define which pin is connected to the 12 chip's !RESET pin. If specified, the driver will 13 assert a hardware reset at probe time. 14 - adi,pll-mode-gpios: An array of two GPIO specs to describe the GPIOs 15 the ADAU's PLL config pins are connected to. 19 - adi,pin-config: An array of 12 numerical values selecting one of the 23 - avdd-supply: Power supply for AVDD, providing 3.3V 24 - dvdd-supply: Power supply for DVDD, providing 3.3V [all …]
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/freebsd/sys/contrib/device-tree/Bindings/clock/ |
H A D | silabs,si5341.txt | 6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf 8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf 10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf 13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which 20 The driver can be used in "as is" mode, reading the current settings from the 21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not 33 - compatible: shall be one of the following: 34 "silabs,si5340" - Si5340 A/B/C/D 35 "silabs,si5341" - Si5341 A/B/C/D 36 "silabs,si5342" - Si5342 A/B/C/D [all …]
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
H A D | sa8540p-ride.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 7 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 13 #include "sa8540p-pmics.dtsi" 17 compatible = "qcom,sa8540p-rid [all...] |
H A D | sa8295p-adp.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 7 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 11 #include <dt-bindings/spmi/spmi.h> 14 #include "sa8540p-pmics.dtsi" 18 compatible = "qcom,sa8295p-adp", "qcom,sa8540p"; 25 stdout-path = "serial0:115200n8"; 28 dp2-connector { 29 compatible = "dp-connector"; [all …]
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H A D | sa8155p-adp.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 6 /dts-v1/; 8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 9 #include <dt-bindings/gpio/gpio.h> 16 compatible = "qcom,sa8155p-adp", "qcom,sa8155p"; 24 stdout-path = "serial0:115200n8"; 27 vreg_3p3: vreg-3p3-regulator { 28 compatible = "regulator-fixed"; 29 regulator-name = "vreg_3p3"; 30 regulator-min-microvolt = <3300000>; [all …]
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H A D | sdm850-samsung-w737.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 8 /dts-v1/; 10 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 11 #include <dt-bindings/input/gpio-keys.h> 12 #include <dt-binding [all...] |
H A D | sc8280xp-crd.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 7 /dts-v1/; 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 13 #include "sc8280xp-pmics.dtsi" 17 compatible = "qcom,sc8280xp-cr [all...] |
H A D | sc8180x-lenovo-flex-5g.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 7 /dts-v1/; 9 #include <dt-bindings/firmware/qcom,scm.h> 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-binding [all...] |
H A D | sc8180x-primus.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 7 /dts-v1/; 9 #include <dt-bindings/firmware/qcom,scm.h> 10 #include <dt-bindings/gpio/gpio.h> 11 #include <dt-binding [all...] |
H A D | sc7280-qcard.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 14 #include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h> 15 #include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h> 16 #include <dt-binding [all...] |
H A D | sm8350-hdk.dts | 1 // SPDX-License-Identifier: BSD-3-Clause 3 * Copyright (c) 2020-2021, Linaro Limited 6 /dts-v1/; 8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h> 19 compatible = "qcom,sm8350-hdk", "qcom,sm8350"; 20 chassis-typ [all...] |
/freebsd/sys/dev/firmware/xilinx/ |
H A D | pm_defs.h | 2 * Copyright (c) 2013-2022, ARM Limited and Contributors. All rights reserved. 4 * SPDX-License-Identifier: BSD-3-Clause 117 /* PLL control API functions */ 304 * @PMF_SHUTDOWN_TYPE_RESET: reset/reboot 325 * @PM_PLL_PARAM_DIV2: Enable for divide by 2 function inside the PLL 326 * @PM_PLL_PARAM_FBDIV: Feedback divisor integer portion for the PLL 327 * @PM_PLL_PARAM_DATA: Feedback divisor fractional portion for the PLL 328 * @PM_PLL_PARAM_PRE_SRC: Clock source for PLL input 329 * @PM_PLL_PARAM_POST_SRC: Clock source for PLL Bypass mode 332 * @PM_PLL_PARAM_LFHF: PLL loop filter high frequency capacitor control [all …]
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/freebsd/sys/dev/ath/ath_hal/ar5312/ |
H A D | ar5312_reset.c | 1 /*- 2 * SPDX-License-Identifier: ISC 4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 62 #define V(r, c) (ia)->data[((r)*(ia)->cols) + (c)] in write_common() 66 for (i = 0; i < ia->rows; i++) { in write_common() 69 /* On channel change, don't reset the PCU registers */ in write_common() 81 * Places the device in and out of reset and then places sane 83 * vectors (as determined by the mode), and station configuration 86 * a HW Reset during channel change. [all …]
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/freebsd/sys/dev/usb/serial/ |
H A D | umcs.h | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 50 #define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong 52 #define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong 67 #define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */ 69 #define MCS7840_DEV_REG_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */ 70 #define MCS7840_DEV_REG_CLOCK_MUX 0x12 /* PLL input clock & Interrupt 78 /* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */ 109 #define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port 112 #define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port [all …]
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/freebsd/sys/arm64/rockchip/ |
H A D | rk3568_combphy.c | 1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 49 #include <contrib/device-tree/include/dt-bindings/phy/phy.h> 57 {"rockchip,rk3568-naneng-combphy", 1}, 72 int mode; member 174 switch (sc->mode) { in rk3568_combphy_enable() 179 bus_write_4(sc->mem, PHYREG7, in rk3568_combphy_enable() 183 bus_write_4(sc->mem, PHYREG15, in rk3568_combphy_enable() 184 bus_read_4(sc->mem, PHYREG15) | PHYREG15_CTLE_EN); in rk3568_combphy_enable() 187 SYSCON_WRITE_4(sc->pipe_phy_grf, PIPE_PHY_GRF_PIPE_CON3, in rk3568_combphy_enable() [all …]
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