Lines Matching +full:pll +full:- +full:reset +full:- +full:mode

6  - compatible: should be "rockchip,<name>-gamc"
7    "rockchip,px30-gmac":   found on PX30 SoCs
8    "rockchip,rk3128-gmac": found on RK312x SoCs
9    "rockchip,rk3228-gmac": found on RK322x SoCs
10    "rockchip,rk3288-gmac": found on RK3288 SoCs
11    "rockchip,rk3328-gmac": found on RK3328 SoCs
12    "rockchip,rk3366-gmac": found on RK3366 SoCs
13    "rockchip,rk3368-gmac": found on RK3368 SoCs
14    "rockchip,rk3399-gmac": found on RK3399 SoCs
15    "rockchip,rv1108-gmac": found on RV1108 SoCs
16  - reg: addresses and length of the register sets for the device.
17  - interrupts: Should contain the GMAC interrupts.
18  - interrupt-names: Should contain the interrupt names "macirq".
19  - rockchip,grf: phandle to the syscon grf used to control speed and mode.
20  - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.
21 	   <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC
28  - clock-names: One name for each entry in the clocks property.
29  - phy-mode: See ethernet.txt file in the same directory.
30  - pinctrl-names: Names corresponding to the numbered pinctrl states.
31  - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
32  - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
33    is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
36  - snps,reset-gpio       gpio number for phy reset.
37  - snps,reset-active-low boolean flag to indicate if phy reset is active low.
38  - assigned-clocks: main clock, should be <&cru SCLK_MAC>;
39  - assigned-clock-parents = parent of main clock.
43  - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
44  - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
45  - phy-supply: phandle to a regulator if the PHY needs one
50 	compatible = "rockchip,rk3288-gmac";
53 	interrupt-names = "macirq";
59 	clock-names = "stmmaceth",
63 	phy-mode = "rgmii";
64 	pinctrl-names = "default";
65 	pinctrl-0 = <&rgmii_pins /*&rmii_pins*/>;
68 	snps,reset-gpio = <&gpio4 7 0>;
69 	snps,reset-active-low;
71 	assigned-clocks = <&cru SCLK_MAC>;
72 	assigned-clock-parents = <&ext_gmac>;