Lines Matching +full:pll +full:- +full:reset +full:- +full:mode
6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
20 The driver can be used in "as is" mode, reading the current settings from the
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
36 "silabs,si5342" - Si5342 A/B/C/D
37 "silabs,si5344" - Si5344 A/B/C/D
38 "silabs,si5345" - Si5345 A/B/C/D
39 - reg: i2c device address, usually 0x74
40 - #clock-cells: from common clock binding; shall be set to 2.
43 - clocks: from common clock binding; list of parent clock handles,
46 - clock-names: One of: "xtal", "in0", "in1", "in2"
49 - vdd-supply: Regulator node for VDD
50 - vdda-supply: Regulator node for VDDA
51 - vdds-supply: Regulator node for VDDS
52 - silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
53 feedback divider. Must be such that the PLL output is in the valid range. For
54 example, to create 14GHz from a 48MHz xtal, use m-num=14000 and m-den=48. Only
56 If these are not specified, and the PLL is not yet programmed when the driver
57 probes, the PLL will be set to 14GHz.
58 - silabs,reprogram: When present, the driver will always assume the device must
59 be initialized, and always performs the soft-reset routine. Since this will
62 - silabs,xaxb-ext-clk: When present, indicates that the XA/XB pins are used
63 in EXTCLK (external reference clock) rather than XTAL (crystal) mode.
64 - interrupts: Interrupt for INTRb pin.
65 - silabs,iovdd-33: When present, indicates that the I2C lines are using 3.3V
67 - vddoX-supply (where X is an output index): Regulator node for VDDO for the
70 - #address-cells: shall be set to 1.
71 - #size-cells: shall be set to 0.
83 - reg: number of clock output.
86 - silabs,format: Output format, one of:
88 2 = low-power (defaults to HCSL levels)
90 - silabs,common-mode: Manually override output common mode, see [2] for values
91 - silabs,amplitude: Manually override output amplitude, see [2] for values
92 - silabs,synth-master: boolean. If present, this output is allowed to change the
94 - silabs,silabs,disable-high: boolean. If set, the clock output is driven HIGH
101 compatible = "fixed-clock";
102 #clock-cells = <0>;
103 clock-frequency = <48000000>;
106 i2c-master-node {
108 si5341: clock-generator@74 {
111 #clock-cells = <2>;
112 #address-cells = <1>;
113 #size-cells = <0>;
115 clock-names = "xtal";
117 silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
118 silabs,pll-m-den = <48>;
119 silabs,reprogram; /* Chips are not programmed, always reset */
124 silabs,common-mode = <3>;
126 silabs,synth-master;
136 silabs,common-mode = <13>;
147 silabs,common-mode = <11>;
153 some-video-node {
155 clock-names = "pixel";
159 assigned-clocks = <&si5341 0 7>, <&si5341 1 3>;
160 assigned-clock-parents = <&si5341 1 3>;
162 assigned-clock-rates = <148500000>, <594000000>;
165 some-audio-node {
166 clock-names = "i2s-clk";
169 * since output 0 is a synth-master, the synth will be automatically set
173 assigned-clocks = <&si5341 0 0>;
174 assigned-clock-parents = <&si5341 1 2>;