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/linux/drivers/video/fbdev/aty/
H A Dmach64_accel.c1 // SPDX-License-Identifier: GPL-2.0
17 /* this is for DMA GUI engine! work in progress */
42 /* reset engine */ in aty_reset_engine()
46 /* enable engine */ in aty_reset_engine()
49 /* ensure engine is not locked up by clearing any FIFO or */ in aty_reset_engine()
54 par->fifo_space = 0; in aty_reset_engine()
73 pitch_value = info->fix.line_length / (info->var.bits_per_pixel / 8); in aty_init_engine()
74 vxres = info->var.xres_virtual; in aty_init_engine()
76 if (info->var.bits_per_pixel == 24) { in aty_init_engine()
77 /* In 24 bpp, the engine is in 8 bpp - this requires that all */ in aty_init_engine()
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/linux/drivers/media/platform/samsung/s3c-camif/
H A Dcamif-core.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 #include <media/media-entity.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-dev.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-mediabus.h>
25 #include <media/videobuf2-v4l2.h>
26 #include <media/drv-intf/s3c_camif.h>
28 #define S3C_CAMIF_DRIVER_NAME "s3c-camif"
39 #define S3C2450_CAMIF_IP_REV 0x30 /* 3.0 - not implemented, not tested */
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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_backend.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
14 #include <linux/dma-mapping.h>
35 /* backend <-> TCON muxing selection done in backend */
48 static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine) in sun4i_backend_apply_color_correction() argument
55 regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG, in sun4i_backend_apply_color_correction()
59 regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i), in sun4i_backend_apply_color_correction()
63 static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine) in sun4i_backend_disable_color_correction() argument
68 regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG, in sun4i_backend_disable_color_correction()
72 static void sun4i_backend_commit(struct sunxi_engine *engine, in sun4i_backend_commit() argument
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H A Dsun4i_tv.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
55 #define SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(dac, x) ((4 - (x)) << (dac * 3))
138 u16 pixel; member
198 .field = false, .line = 14, .pixel = 12,
202 .field = true, .line = 13, .pixel = 12,
256 if (tv_mode->tv_mode == mode) in sun4i_tv_find_tv_by_mode()
267 struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc); in sun4i_tv_disable()
271 regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG, in sun4i_tv_disable()
275 sunxi_engine_disable_color_correction(crtc->engine); in sun4i_tv_disable()
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/linux/drivers/gpu/drm/
H A Ddrm_writeback.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/dma-fence.h>
57 * Write-only object property storing a DRM_MODE_OBJECT_FB: it stores the
65 * Immutable blob property to store the supported pixel formats table. The
67 * Userspace can use this blob to find out what pixel formats are supported
68 * by the connector's writeback engine.
73 * writeback is finished. The value should be the address of a 32-bit
80 * out-fence for the commit and use it appropriately.
84 #define fence_to_wb_connector(x) container_of(x->lock, \
93 return wb_connector->base.dev->driver->name; in drm_writeback_fence_get_driver_name()
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/linux/Documentation/devicetree/bindings/media/
H A Dnvidia,tegra-vde.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Video Decoder Engine
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
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H A Dnxp,dw100.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xavier Roumegue <xavier.roumegue@oss.nxp.com>
12 description: |-
13 The Dewarp Engine provides high-performance dewarp processing for the
15 and wide angle lenses. It is implemented with a line/tile-cache based
18 The engine can be used to perform scaling, cropping and pixel format
24 - nxp,imx8mp-dw100
34 - description: The AXI clock
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-libra-rdk-fpsc-lvds-etml1010g3dra.dtso1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/clock/imx8mp-clock.h>
9 /dts-v1/;
13 brightness-levels = <0 8 16 32 64 128 255>;
14 default-brightness-level = <8>;
15 enable-gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
16 num-interpolated-steps = <2>;
26 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>;
27 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
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/linux/drivers/video/fbdev/i810/
H A Di810_accel.c1 /*-*- linux-c -*-
2 * linux/drivers/video/i810_accel.c -- Hardware Acceleration
26 i810_writel(par->cur_tail, par->iring.virtual, n); \
27 par->cur_tail += 4; \
28 par->cur_tail &= RING_SIZE_MASK; \
35 /* BLT Engine Routines */
51 * wait_for_space - check ring buffer free space
61 struct i810fb_par *par = info->par; in wait_for_space()
63 u8 __iomem *mmio = par->mmio_start_virtual; in wait_for_space()
65 tail = par->cur_tail; in wait_for_space()
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/linux/drivers/media/platform/nxp/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
21 tristate "NXP i.MX8MQ MIPI CSI-2 receiver"
28 Video4Linux2 driver for the MIPI CSI-2 receiver found on the i.MX8MQ
32 tristate "NXP MIPI CSI-2 CSIS receiver found on i.MX7 and i.MX8 models"
39 Video4Linux2 sub-device driver for the MIPI CSI-2 CSIS receiver
42 source "drivers/media/platform/nxp/imx8-isi/Kconfig"
47 tristate "NXP i.MX Pixel Pipeline (PXP)"
53 The i.MX Pixel Pipeline is a memory-to-memory engine for scaling,
57 tristate "NXP MX2 eMMa-PrP support"
69 source "drivers/media/platform/nxp/imx-jpeg/Kconfig"
/linux/Documentation/devicetree/bindings/display/
H A Darm,malidp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm Mali Display Processor (Mali-DP)
10 - Liviu Dudau <Liviu.Dudau@arm.com>
11 - Andre Przywara <andre.przywara@arm.com>
22 - arm,mali-dp500
23 - arm,mali-dp550
24 - arm,mali-dp650
31 - description:
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/linux/include/uapi/linux/
H A Domap3isp.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
5 * TI OMAP3 ISP - User-space API
25 * 02110-1301 USA
38 * VIDIOC_OMAP3ISP_PRV_CFG: Set preview engine configuration
41 * VIDIOC_OMAP3ISP_AF_CFG: Set auto-focus module configuration
121 * struct omap3isp_h3a_aewb_config - AE AWB configuration reset values
123 * @win_height: Window Height. Range 2 - 256, even values only.
124 * @win_width: Window Width. Range 6 - 256, even values only.
125 * @ver_win_count: Vertical Window Count. Range 1 - 128.
126 * @hor_win_count: Horizontal Window Count. Range 1 - 36.
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/linux/drivers/gpu/drm/amd/display/include/
H A Dbios_parser_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
158 /* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should
159 * be pixel clock * deep_color_ratio (in KHz)
197 /* Input: Signal Type - to be converted to Encoder mode */
201 /* Input: Pixel Clock (requested Pixel clock based on Video timing
205 /* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */
207 /* Output: If non-zero, this refDiv value should be used to calculate
210 /* Output: If non-zero, this postDiv value should be used to calculate
220 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
222 /* Adjusted Pixel Clock (after VBIOS exec table)
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/linux/Documentation/devicetree/bindings/display/mediatek/
H A Dmediatek,padding.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
16 width of a layer to be 2-pixel-align, or 4-pixel-align when ETHDR is enabled,
24 - enum:
25 - mediatek,mt8188-disp-padding
26 - mediatek,mt8195-mdp3-padding
27 - items:
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/linux/drivers/video/fbdev/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
14 a well-defined interface, so the software doesn't need to know
15 anything about the low-level (hardware register) stuff.
21 On several non-X86 architectures, the frame buffer device is the
29 and the Framebuffer-HOWTO at
30 <http://www.munted.org.uk/programming/Framebuffer-HOWTO-1.3.html> for more
40 are compiling a kernel for a non-x86 architecture.
46 device-aware may cause unexpected results. If unsure, say N.
57 Common utility functions useful to fbdev drivers of VGA-based
82 If you have a PCI-based system, this enables support for these
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H A Datmel_lcdfb.c13 #include <linux/dma-mapping.h>
69 #define lcdc_readl(sinfo, reg) __raw_readl((sinfo)->mmio+(reg))
70 #define lcdc_writel(sinfo, reg, val) __raw_writel((val), (sinfo)->mmio+(reg))
107 /* some bl->props field just changed */
140 if (sinfo->backlight) in init_backlight()
146 bl = backlight_device_register("backlight", &sinfo->pdev->dev, sinfo, in init_backlight()
149 dev_err(&sinfo->pdev->dev, "error %ld on backlight register\n", in init_backlight()
153 sinfo->backlight = bl; in init_backlight()
155 bl->props.power = BACKLIGHT_POWER_ON; in init_backlight()
156 bl->props.brightness = atmel_bl_get_brightness(bl); in init_backlight()
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/linux/drivers/media/platform/xilinx/
H A Dxilinx-dma.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2013-2015 Ideas on Board
6 * Copyright (C) 2013-2015 Xilinx, Inc.
20 #include <media/media-entity.h>
21 #include <media/v4l2-dev.h>
22 #include <media/videobuf2-v4l2.h>
29 * struct xvip_pipeline - Xilinx Video IP pipeline structure
35 * @output: DMA engine at the output of the pipeline
59 * struct xvip_dma - Video DMA channel
67 * @format: active V4L2 pixel format
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/linux/Documentation/admin-guide/media/
H A Dplatform-cardlist.rst1 .. SPDX-License-Identifier: GPL-2.0
17 am437x-vpfe TI AM437x VPFE
18 aspeed-video Aspeed AST2400 and AST2500
19 atmel-isc ATMEL Image Sensor Controller (ISC)
20 atmel-isi ATMEL Image Sensor Interface (ISI)
24 cdns-csi2rx Cadence MIPI-CSI2 RX Controller
25 cdns-csi2tx Cadence MIPI-CSI2 TX Controller
26 coda-vpu Chips&Media Coda multi-standard codec IP
29 exynos-fimc-is EXYNOS4x12 FIMC-IS (Imaging Subsystem)
30 exynos-fimc-lite EXYNOS FIMC-LITE camera interface
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/linux/arch/arm/boot/dts/mediatek/
H A Dmt7623n.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright © 2017-2020 MediaTek Inc.
10 #include <dt-bindings/memory/mt2701-larb-port.h>
19 compatible = "mediatek,mt7623-g3dsys",
20 "mediatek,mt2701-g3dsys",
23 #clock-cells = <1>;
24 #reset-cells = <1>;
28 compatible = "mediatek,mt7623-mali", "arm,mali-450";
41 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
46 clock-names = "bus", "core";
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/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
22 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
23 * produced by non-pipelined state commands), software needs to first
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
27 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
33 * BEFORE the pipe-control with a post-sync op and no write-cache
41 * - Render Target Cache Flush Enable ([12] of DW1)
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
57 enc110->base.ctx
59 enc110->base.ctx->logger
62 (enc110->link_regs->reg)
65 (enc110->aux_regs->reg)
68 (enc110->hpd_regs->reg)
75 * ASIC-dependent, actual values for register programming
91 (reg + enc110->offsets.dig)
94 (reg + enc110->offsets.dp)
127 struct dc_bios *bp = enc110->base.ctx->dc_bios; in link_transmitter_control()
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/linux/Documentation/devicetree/bindings/display/hisilicon/
H A Dhisi-ade.txt1 Device-Tree bindings for hisilicon ADE display controller driver
3 ADE (Advanced Display Engine) is the display controller which grab image
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
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/linux/drivers/video/fbdev/core/
H A Dfb_fillrect.h1 /* SPDX-License-Identifier: GPL-2.0-only
3 * Generic bit area filler and twister engine for packed pixel framebuffers
9 * Copyright (C) 2000 James Simmons (jsimmons@linux-fbdev.org)
20 * reverse pixel order in a byte (<8 BPP), word length of 32/64 bits,
21 * bits per pixel from 1 to the word length. Handles line lengths at byte
24 * Optimized path for power of two bits per pixel modes.
44 return pattern->pixels; in fb_pattern_get()
50 return swab_long(pattern->pixels); in fb_pattern_get_reverse()
62 pattern->pixels = fb_left(pattern->pixels, pattern->left) in fb_pattern_rotate()
63 | fb_right(pattern->pixels, pattern->right); in fb_pattern_rotate()
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/linux/drivers/gpu/drm/amd/display/dc/resource/dce60/
H A Ddce60_resource.c115 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
116 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
118 - mmDPG_PIPE_ARBITRATION_CONTROL3),
121 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
122 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
124 - mmDPG_PIPE_ARBITRATION_CONTROL3),
127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
128 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
130 - mmDPG_PIPE_ARBITRATION_CONTROL3),
133 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
[all …]
/linux/drivers/video/fbdev/via/
H A Daccel.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
7 #include <linux/via-core.h>
11 * Figure out an appropriate bytes-per-pixel setting.
13 static int viafb_set_bpp(void __iomem *engine, u8 bpp) in viafb_set_bpp() argument
19 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc; in viafb_set_bpp()
32 return -EINVAL; in viafb_set_bpp()
34 writel(gemode, engine + VIA_REG_GEMODE); in viafb_set_bpp()
39 static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height, in hw_bitblt_1() argument
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