1*2b743164SYannic Moog// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2*2b743164SYannic Moog/* 3*2b743164SYannic Moog * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4*2b743164SYannic Moog */ 5*2b743164SYannic Moog 6*2b743164SYannic Moog#include <dt-bindings/gpio/gpio.h> 7*2b743164SYannic Moog#include <dt-bindings/clock/imx8mp-clock.h> 8*2b743164SYannic Moog 9*2b743164SYannic Moog/dts-v1/; 10*2b743164SYannic Moog/plugin/; 11*2b743164SYannic Moog 12*2b743164SYannic Moog&backlight_lvds0 { 13*2b743164SYannic Moog brightness-levels = <0 8 16 32 64 128 255>; 14*2b743164SYannic Moog default-brightness-level = <8>; 15*2b743164SYannic Moog enable-gpios = <&gpio5 23 GPIO_ACTIVE_LOW>; 16*2b743164SYannic Moog num-interpolated-steps = <2>; 17*2b743164SYannic Moog pwms = <&pwm1 0 66667 0>; 18*2b743164SYannic Moog status = "okay"; 19*2b743164SYannic Moog}; 20*2b743164SYannic Moog 21*2b743164SYannic Moog&lcdif2 { 22*2b743164SYannic Moog status = "okay"; 23*2b743164SYannic Moog}; 24*2b743164SYannic Moog 25*2b743164SYannic Moog&lvds_bridge { 26*2b743164SYannic Moog assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, <&clk IMX8MP_VIDEO_PLL1>; 27*2b743164SYannic Moog assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 28*2b743164SYannic Moog /* 29*2b743164SYannic Moog * The LVDS panel uses 72.4 MHz pixel clock, set IMX8MP_VIDEO_PLL1 to 30*2b743164SYannic Moog * 72.4 * 7 = 506.8 MHz so the LDB serializer and LCDIFv3 scanout 31*2b743164SYannic Moog * engine can reach accurate pixel clock of exactly 72.4 MHz. 32*2b743164SYannic Moog */ 33*2b743164SYannic Moog assigned-clock-rates = <0>, <506800000>; 34*2b743164SYannic Moog status = "okay"; 35*2b743164SYannic Moog}; 36*2b743164SYannic Moog 37*2b743164SYannic Moog&panel0_lvds { 38*2b743164SYannic Moog compatible = "edt,etml1010g3dra"; 39*2b743164SYannic Moog status = "okay"; 40*2b743164SYannic Moog}; 41*2b743164SYannic Moog 42*2b743164SYannic Moog&pwm1 { 43*2b743164SYannic Moog status = "okay"; 44*2b743164SYannic Moog}; 45