Lines Matching +full:pixel +full:- +full:engine
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
7 #include <linux/via-core.h>
11 * Figure out an appropriate bytes-per-pixel setting.
13 static int viafb_set_bpp(void __iomem *engine, u8 bpp) in viafb_set_bpp() argument
19 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc; in viafb_set_bpp()
32 return -EINVAL; in viafb_set_bpp()
34 writel(gemode, engine + VIA_REG_GEMODE); in viafb_set_bpp()
39 static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height, in hw_bitblt_1() argument
49 return -EINVAL; in hw_bitblt_1()
55 src_x += width - 1; in hw_bitblt_1()
56 dst_x += width - 1; in hw_bitblt_1()
60 src_y += height - 1; in hw_bitblt_1()
61 dst_y += height - 1; in hw_bitblt_1()
75 return -EINVAL; in hw_bitblt_1()
79 ret = viafb_set_bpp(engine, dst_bpp); in hw_bitblt_1()
88 return -EINVAL; in hw_bitblt_1()
91 writel(tmp, engine + 0x08); in hw_bitblt_1()
97 return -EINVAL; in hw_bitblt_1()
100 writel(tmp, engine + 0x0C); in hw_bitblt_1()
102 if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) { in hw_bitblt_1()
105 return -EINVAL; in hw_bitblt_1()
107 tmp = (width - 1) | ((height - 1) << 16); in hw_bitblt_1()
108 writel(tmp, engine + 0x10); in hw_bitblt_1()
111 writel(fg_color, engine + 0x18); in hw_bitblt_1()
114 writel(bg_color, engine + 0x1C); in hw_bitblt_1()
121 return -EINVAL; in hw_bitblt_1()
124 writel(tmp, engine + 0x30); in hw_bitblt_1()
130 return -EINVAL; in hw_bitblt_1()
133 writel(tmp, engine + 0x34); in hw_bitblt_1()
142 return -EINVAL; in hw_bitblt_1()
144 tmp = VIA_PITCH_ENABLE | (tmp >> 3) | (dst_pitch << (16 - 3)); in hw_bitblt_1()
145 writel(tmp, engine + 0x38); in hw_bitblt_1()
158 writel(ge_cmd, engine); in hw_bitblt_1()
167 writel(src_mem[i], engine + VIA_MMIO_BLTBASE); in hw_bitblt_1()
172 static int hw_bitblt_2(void __iomem *engine, u8 op, u32 width, u32 height, in hw_bitblt_2() argument
182 return -EINVAL; in hw_bitblt_2()
188 src_x += width - 1; in hw_bitblt_2()
189 dst_x += width - 1; in hw_bitblt_2()
193 src_y += height - 1; in hw_bitblt_2()
194 dst_y += height - 1; in hw_bitblt_2()
208 return -EINVAL; in hw_bitblt_2()
212 ret = viafb_set_bpp(engine, dst_bpp); in hw_bitblt_2()
223 return -EINVAL; in hw_bitblt_2()
225 tmp = (tmp >> 3) | (dst_pitch << (16 - 3)); in hw_bitblt_2()
226 writel(tmp, engine + 0x08); in hw_bitblt_2()
228 if ((width - 1) & 0xFFFFF000 || (height - 1) & 0xFFFFF000) { in hw_bitblt_2()
231 return -EINVAL; in hw_bitblt_2()
233 tmp = (width - 1) | ((height - 1) << 16); in hw_bitblt_2()
234 writel(tmp, engine + 0x0C); in hw_bitblt_2()
239 return -EINVAL; in hw_bitblt_2()
242 writel(tmp, engine + 0x10); in hw_bitblt_2()
247 return -EINVAL; in hw_bitblt_2()
250 writel(tmp, engine + 0x14); in hw_bitblt_2()
257 return -EINVAL; in hw_bitblt_2()
260 writel(tmp, engine + 0x18); in hw_bitblt_2()
266 return -EINVAL; in hw_bitblt_2()
269 writel(tmp, engine + 0x1C); in hw_bitblt_2()
273 writel(fg_color, engine + 0x58); in hw_bitblt_2()
275 writel(fg_color, engine + 0x4C); in hw_bitblt_2()
276 writel(bg_color, engine + 0x50); in hw_bitblt_2()
290 writel(ge_cmd, engine); in hw_bitblt_2()
299 writel(src_mem[i], engine + VIA_MMIO_BLTBASE); in hw_bitblt_2()
306 struct viafb_par *viapar = info->par; in viafb_setup_engine()
307 void __iomem *engine; in viafb_setup_engine() local
308 u32 chip_name = viapar->shared->chip_info.gfx_chip_name; in viafb_setup_engine()
310 engine = viapar->shared->vdev->engine_mmio; in viafb_setup_engine()
311 if (!engine) { in viafb_setup_engine()
314 return -ENOMEM; in viafb_setup_engine()
328 viapar->shared->hw_bitblt = hw_bitblt_1; in viafb_setup_engine()
333 viapar->shared->hw_bitblt = hw_bitblt_2; in viafb_setup_engine()
336 viapar->shared->hw_bitblt = NULL; in viafb_setup_engine()
339 viapar->fbmem_free -= CURSOR_SIZE; in viafb_setup_engine()
340 viapar->shared->cursor_vram_addr = viapar->fbmem_free; in viafb_setup_engine()
341 viapar->fbmem_used += CURSOR_SIZE; in viafb_setup_engine()
343 viapar->fbmem_free -= VQ_SIZE; in viafb_setup_engine()
344 viapar->shared->vq_vram_addr = viapar->fbmem_free; in viafb_setup_engine()
345 viapar->fbmem_used += VQ_SIZE; in viafb_setup_engine()
354 * As for the size: the engine can handle three frames, in viafb_setup_engine()
357 viapar->shared->vdev->camera_fbmem_size = 3*VGA_HEIGHT*VGA_WIDTH*2; in viafb_setup_engine()
358 viapar->fbmem_free -= viapar->shared->vdev->camera_fbmem_size; in viafb_setup_engine()
359 viapar->fbmem_used += viapar->shared->vdev->camera_fbmem_size; in viafb_setup_engine()
360 viapar->shared->vdev->camera_fbmem_offset = viapar->fbmem_free; in viafb_setup_engine()
369 void __iomem *engine = viapar->shared->vdev->engine_mmio; in viafb_reset_engine() local
372 vq_len, chip_name = viapar->shared->chip_info.gfx_chip_name; in viafb_reset_engine()
374 /* Initialize registers to reset the 2D engine */ in viafb_reset_engine()
375 switch (viapar->shared->chip_info.twod_engine) { in viafb_reset_engine()
384 writel(0x0, engine + i); in viafb_reset_engine()
393 writel(0x00100000, engine + VIA_REG_CR_TRANSET); in viafb_reset_engine()
394 writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE); in viafb_reset_engine()
395 writel(0x02000000, engine + VIA_REG_CR_TRANSPACE); in viafb_reset_engine()
399 writel(0x00100000, engine + VIA_REG_TRANSET); in viafb_reset_engine()
400 writel(0x00000000, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
401 writel(0x00333004, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
402 writel(0x60000000, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
403 writel(0x61000000, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
404 writel(0x62000000, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
405 writel(0x63000000, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
406 writel(0x64000000, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
407 writel(0x7D000000, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
409 writel(0xFE020000, engine + VIA_REG_TRANSET); in viafb_reset_engine()
410 writel(0x00000000, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
415 vq_start_addr = viapar->shared->vq_vram_addr; in viafb_reset_engine()
416 vq_end_addr = viapar->shared->vq_vram_addr + VQ_SIZE - 1; in viafb_reset_engine()
435 writel(0x00100000, engine + VIA_REG_CR_TRANSET); in viafb_reset_engine()
436 writel(vq_high, engine + VIA_REG_CR_TRANSPACE); in viafb_reset_engine()
437 writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE); in viafb_reset_engine()
438 writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE); in viafb_reset_engine()
439 writel(vq_len, engine + VIA_REG_CR_TRANSPACE); in viafb_reset_engine()
440 writel(0x74301001, engine + VIA_REG_CR_TRANSPACE); in viafb_reset_engine()
441 writel(0x00000000, engine + VIA_REG_CR_TRANSPACE); in viafb_reset_engine()
444 writel(0x00FE0000, engine + VIA_REG_TRANSET); in viafb_reset_engine()
445 writel(0x080003FE, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
446 writel(0x0A00027C, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
447 writel(0x0B000260, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
448 writel(0x0C000274, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
449 writel(0x0D000264, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
450 writel(0x0E000000, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
451 writel(0x0F000020, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
452 writel(0x1000027E, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
453 writel(0x110002FE, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
454 writel(0x200F0060, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
456 writel(0x00000006, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
457 writel(0x40008C0F, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
458 writel(0x44000000, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
459 writel(0x45080C04, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
460 writel(0x46800408, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
462 writel(vq_high, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
463 writel(vq_start_low, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
464 writel(vq_end_low, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
465 writel(vq_len, engine + VIA_REG_TRANSPACE); in viafb_reset_engine()
470 writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE); in viafb_reset_engine()
471 writel(0x0, engine + VIA_REG_CURSOR_POS); in viafb_reset_engine()
472 writel(0x0, engine + VIA_REG_CURSOR_ORG); in viafb_reset_engine()
473 writel(0x0, engine + VIA_REG_CURSOR_BG); in viafb_reset_engine()
474 writel(0x0, engine + VIA_REG_CURSOR_FG); in viafb_reset_engine()
480 struct viafb_par *viapar = info->par; in viafb_show_hw_cursor()
481 u32 temp, iga_path = viapar->iga_path; in viafb_show_hw_cursor()
483 temp = readl(viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE); in viafb_show_hw_cursor()
500 writel(temp, viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE); in viafb_show_hw_cursor()
505 struct viafb_par *viapar = info->par; in viafb_wait_engine_idle()
508 void __iomem *engine = viapar->shared->vdev->engine_mmio; in viafb_wait_engine_idle() local
510 switch (viapar->shared->chip_info.twod_engine) { in viafb_wait_engine_idle()
517 while (!(readl(engine + VIA_REG_STATUS) & in viafb_wait_engine_idle()
526 while ((readl(engine + VIA_REG_STATUS) & mask) && (loop < MAXLOOP)) { in viafb_wait_engine_idle()