non\-cacheable (full) in projects: linux

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/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A D	cache.json	5 …s transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill re… 35 … instruction stream was being modified by another processor in an MP system - typically a highly u… 52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.", 58 …be (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cr… 64 …iting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cr… 75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A D	cache.json	5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …riefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
H A D	memory.json	5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St… 6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older … 12 …"BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succee… 18 …"BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeed… 24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 36 … "BriefDescription": "The number of retired CLFLUSH instructions. This is a non-speculative event." 46 …"BriefDescription": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and… 84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full.", 91 …esses, although these are generally rare. Each increment represents an eight-byte access, although… 258 "BriefDescription": "Total Page Table Walks on I-side.", [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A D	cache.json	5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har… 11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.", 17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.", 23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.", 29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request… 35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.", 41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a… 64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.", 70 …riefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable… 76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.", [all …]
H A D	memory.json	5 …"BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. St… 6 …-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older … 12 …"BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succee… 18 …"BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeed… 24 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.", 84 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full." 90 …esses, although these are generally rare. Each increment represents an eight-byte access, although… 197 "BriefDescription": "Total Page Table Walks on I-side.", 215 "BriefDescription": "Total Page Table Walks on D-side.", 262 … the processor core. Software PREFETCH instruction saw a match on an already-allocated miss reques…
/linux/arch/riscv/include/asm/
H A D	pgtable-64.h	`1 /* SPDX-License-Identifier: GPL-2.0-only / 23 #define PGDIR_MASK (~(PGDIR_SIZE - 1)) 25 / p4d is folded into pgd in case of 4-level page table / 32 #define P4D_MASK (~(P4D_SIZE - 1)) 34 / pud is folded into pgd in case of 3-level page table */ 37 #define PUD_MASK (~(PUD_SIZE - 1)) 42 #define PMD_MASK (~(PMD_SIZE - 1)) 98 for (order = NAPOT_ORDER_MAX - 1; \ 99 order >= NAPOT_CONT_ORDER_BASE; order--) 104 #define napot_cont_mask(order) (~(napot_cont_size(order) - 1UL)) [all …]`
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a65-e1/
H A D	memory.json	`30 "PublicDescription": "External memory request to non-cacheable memory", 33 "BriefDescription": "External memory request to non-cacheable memory"`
/linux/tools/perf/pmu-events/arch/x86/broadwellde/
H A D	cache.json	7 "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 25 "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 116 "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", 320 "BriefDescription": "Core-originate [all...]
/linux/tools/perf/pmu-events/arch/x86/broadwellx/
H A D	cache.json	7 "PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 25 "PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.", 116 "PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", 320 "BriefDescription": "Core-originate [all...]
/linux/arch/m68k/include/asm/
H A D	m54xxacr.h	1 /* SPDX-License-Identifier: GPL-2.0 / 47 #define ACR_ADMSK(x) ((((x) - 1) & 0xff000000) >> 8) 51 #define ICACHE_SIZE 0x4000 / instruction - 16k / 52 #define DCACHE_SIZE 0x2000 / data - 8k / 56 #define ICACHE_SIZE 0x8000 / instruction - 32k / 57 #define DCACHE_SIZE 0x8000 / data - 32k / 61 #define ICACHE_SIZE 0x2000 / instruction - 8k / 62 #define DCACHE_SIZE 0x2000 / data - 8k */ 68 #define ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS) 69 #define DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS) [all …]
/linux/tools/arch/powerpc/include/asm/
H A D	barrier.h	`1 /* SPDX-License-Identifier: GPL-2.0 / 15 providing an ordering (separately) for (a) cacheable stores and (b) 16 * loads and stores to non-cacheable memory (e.g. I/O devices).`
/linux/tools/perf/pmu-events/arch/x86/tigerlake/
H A D	cache.json	7 "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.", 16 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 27 "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 36 "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", 45 "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable o [all...]
/linux/arch/powerpc/include/asm/
H A D	barrier.h	`1 /* SPDX-License-Identifier: GPL-2.0 / 8 #include <asm/asm-const.h> 11 #include <asm/ppc-opcode.h> 19 providing an ordering (separately) for (a) cacheable stores and (b) 20 * loads and stores to non-cacheable memory (e.g. I/O devices). 30 * For the smp_ barriers, ordering is for cacheable memory operations 36 * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio. 42 /* The sub-arch has lwsync */ 117 #include <asm-generic/barrier.h>`
/linux/arch/sparc/include/asm/
H A D	viking.h	1 /* SPDX-License-Identifier: GPL-2.0 / 18 ----------------------------------------------------------- 19 * \|impl-vers\| RSV \|TC\|AC\|SP\|BM\|PC\|MBM\|SB\|IC\|DC\|PSO\|RSV\|NF\|ME\| 20 * ----------------------------------------------------------- 21 * 31 24 23-17 16 15 14 13 12 11 10 9 8 7 6-2 1 0 23 * TC: Tablewalk Cacheable -- 0 = Twalks are not cacheable in E-cache 24 * 1 = Twalks are cacheable in E-cache 26 * GNU/Viking will only cache tablewalks in the E-cache (mxcc) if present 28 * for machines lacking an E-cache (ie. in MBUS mode) this bit must 31 * AC: Alternate Cacheable -- 0 = Passthru physical accesses not cacheable [all …]
/linux/arch/powerpc/include/asm/nohash/32/
H A D	pte-85xx.h	`1 /* SPDX-License-Identifier: GPL-2.0 / 14 - PRESENT must* be in the bottom two bits because swap PTEs use 19 /* Definitions for FSL Book-E Cores / 45 cacheable kernel and user pages) and one for non cacheable 56 #include <asm/pgtable-masks.h>`
H A D	pte-44x.h	1 /* SPDX-License-Identifier: GPL-2.0 / 9 Because of the 3 word TLB entries to support 36-bit addressing, 16 * ERPN fields in the TLB. -Matt 19 * easier to move into the TLB from the PTE. -BenH. 29 * RPN................................. - - - - - - ERPN....... 33 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR 45 * - PRESENT must be in the bottom three bits because swap cache 48 * - CACHE COHERENT bit (M) has no effect on original PPC440 cores, 50 * have -some- form of SMP support and so I keep the bit there for 53 * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A D	memory.json	5 …"BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable con… 11 "BriefDescription": "Number of memory load operations dispatched to the load-store unit.", 17 "BriefDescription": "Number of memory store operations dispatched to the load-store unit.", 23 "BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.", 29 "BriefDescription": "Store-to-load-forward (STLF) hits." 34 …"BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer … 64 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pa… 70 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coale… 76 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pa… 82 …"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pa… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A D	pipeline.json	`21 …ion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty… 24 …ion issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty… 57 …Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)", 60 … Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)"`
/linux/tools/perf/pmu-events/arch/x86/goldmont/
H A D	cache.json	20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 33 …from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cac… 176 "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)", 187 "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)", 198 "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)", 558 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th… 564 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t… 569 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th… 575 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t… 580 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th… [all …]
/linux/arch/powerpc/include/asm/nohash/
H A D	pte-e500.h	`1 /* SPDX-License-Identifier: GPL-2.0 / 34 #define _PAGE_WRITETHRU 0x800000 / W: cache write-through / 63 / On 32-bit, we never clear the top part of the PTE / 76 cacheable kernel and user pages) and one for non cacheable 87 #include <asm/pgtable-masks.h>`
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a53/
H A D	memory.json	`10 "BriefDescription": "Non-cacheable external memory request"`
/linux/arch/arm/include/asm/
H A D	pgtable-3level-hwdef.h	1 /* SPDX-License-Identifier: GPL-2.0-only / 3 arch/arm/include/asm/pgtable-3level-hwdef.h 15 * - common 30 * - section 50 #define PMD_SECT_BUFFERED (_AT(pmdval_t, 1) << 2) /* normal non-cacheable / 51 #define PMD_SECT_WT (_AT(pmdval_t, 2) << 2) / normal inner write-through / 52 #define PMD_SECT_WB (_AT(pmdval_t, 3) << 2) / normal inner write-back / 53 #define PMD_SECT_WBWA (_AT(pmdval_t, 7) << 2) / normal inner write-alloc / 73 40-bit physical address supported. 76 #define PHYS_MASK ((1ULL << PHYS_MASK_SHIFT) - 1) [all …]
/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A D	cache.json	20 "BriefDescription": "Cycles code-fetch stalled due to an outstanding ICache miss.", 33 …from the intra-die interconnect (IDI) fabric. The XQ may reject transactions from the L2Q (non-cac… 176 "BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)", 187 "BriefDescription": "Load uops retired that split a cache-line (Precise event capable)", 198 "BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)", 602 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th… 608 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t… 613 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th… 619 …"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss t… 624 …"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss th… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A D	pipeline.json	`33 "PublicDescription": "No operation issued due to the frontend, pre-decode error", 36 "BriefDescription": "No operation issued due to the frontend, pre-decode error" 69 …e event counts for stalls that are caused by missing the cache or where the data is Non-cacheable", 72 …he event counts for stalls that are caused by missing the cache or where the data is Non-cacheable"`
/linux/arch/sh/boot/compressed/
H A D	head_64.S	`27 /* 512 Mb, Cacheable (Write-back), execute, Not User, Ph. Add. / 32 / 512 Mb, Cacheable (Write-back), read/write, Not User, Ph. Add. / 111 From here-on code can be non-PIC.`

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