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/freebsd/sys/contrib/xen/
H A Ddevice_tree_defs.h17 * DT_IRQ_TYPE_NONE - default, unspecified type
18 * DT_IRQ_TYPE_EDGE_RISING - rising edge triggered
19 * DT_IRQ_TYPE_EDGE_FALLING - falling edge triggered
20 * DT_IRQ_TYPE_EDGE_BOTH - rising and falling edge triggered
21 * DT_IRQ_TYPE_LEVEL_HIGH - high level triggered
22 * DT_IRQ_TYPE_LEVEL_LOW - low level triggered
23 * DT_IRQ_TYPE_LEVEL_MASK - Mask to filter out the level bits
24 * DT_IRQ_TYPE_SENSE_MASK - Mask for all the above bits
25 * DT_IRQ_TYPE_INVALID - Use to initialize the type
/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dnvidia,tegra124-soctherm.txt4 or interrupt-based thermal monitoring, CPU and GPU throttling based
10 - compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
11 For Tegra132, must contain "nvidia,tegra132-soctherm".
12 For Tegra210, must contain "nvidia,tegra210-soctherm".
13 - reg : Should contain at least 2 entries for each entry in reg-names:
14 - SOCTHERM register set
15 - Tegra CAR register set: Required for Tegra124 and Tegra210.
16 - CCROC register set: Required for Tegra132.
17 - reg-names : Should contain at least 2 entries:
18 - soctherm-reg
[all …]
/freebsd/contrib/ntp/sntp/libevent/test/
H A Dregress_et.c2 * Copyright (c) 2009-2012 Niels Provos and Nick Mathewson
26 #include "../util-internal.h"
27 #include "event2/event-config.h"
82 struct event_base *base = data->base; in test_edgetriggered()
83 evutil_socket_t *pair = data->pair; in test_edgetriggered()
91 * get edge-triggered behavior. Yuck! Linux 3.1.9 didn't have this in test_edgetriggered()
101 TT_BLATHER(("Checking for edge-triggered events with %s, which should %s" in test_edgetriggered()
102 "support edge-triggering", event_base_get_method(base), in test_edgetriggered()
112 * triggered, we'll only see the event once (since we only see transitions in test_edgetriggered()
114 * do nothing. If we're level triggered, the second invocation of in test_edgetriggered()
[all …]
/freebsd/contrib/libevent/test/
H A Dregress_et.c2 * Copyright (c) 2009-2012 Niels Provos and Nick Mathewson
26 #include "../util-internal.h"
27 #include "event2/event-config.h"
82 struct event_base *base = data->base; in test_edgetriggered()
83 evutil_socket_t *pair = data->pair; in test_edgetriggered()
91 * get edge-triggered behavior. Yuck! Linux 3.1.9 didn't have this in test_edgetriggered()
101 TT_BLATHER(("Checking for edge-triggered events with %s, which should %s" in test_edgetriggered()
102 "support edge-triggering", event_base_get_method(base), in test_edgetriggered()
112 * triggered, we'll only see the event once (since we only see transitions in test_edgetriggered()
114 * do nothing. If we're level triggered, the second invocation of in test_edgetriggered()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/soc/qcom/
H A Dqcom,rpmh-rsc.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/soc/qcom/qcom,rpmh-rsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
16 using a (addr, val) pair and triggered. Messages in the TCS are then sent in
25 A TCS may be triggered from Linux or triggered by the F/W after all the CPUs
27 ACTIVE - Triggered by Linux
28 SLEEP - Triggered by F/W
29 WAKE - Triggered by F/W
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dcavium-octeon-gpio.txt4 - compatible: "cavium,octeon-3860-gpio"
8 - reg: The base address of the GPIO unit's register bank.
10 - gpio-controller: This is a GPIO controller.
12 - #gpio-cells: Must be <2>. The first cell is the GPIO pin.
14 - interrupt-controller: The GPIO controller is also an interrupt
18 - #interrupt-cells: Must be <2>. The first cell is the GPIO pin
21 1 - edge triggered on the rising edge.
22 2 - edge triggered on the falling edge
23 4 - level triggered active high.
24 8 - level triggered active low.
[all …]
H A Dgpio-nmk.txt4 - compatible : Should be "st,nomadik-gpio".
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller.
7 - #gpio-cells : Should be two:
10 - bits[3:0] trigger type and level flags:
11 1 = low-to-high edge triggered.
12 2 = high-to-low edge triggered.
13 4 = active high level-sensitive.
14 8 = active low level-sensitive.
15 - gpio-controller : Marks the device node as a GPIO controller.
[all …]
H A Dnvidia,tegra20-gpio.txt4 - compatible : "nvidia,tegra<chip>-gpio"
5 - reg : Physical base address and length of the controller's registers.
6 - interrupts : The interrupt outputs from the controller. For Tegra20,
9 - #gpio-cells : Should be two. The first cell is the pin number and the
11 - bit 0 specifies polarity (0 for normal, 1 for inverted)
12 - gpio-controller : Marks the device node as a GPIO controller.
13 - #interrupt-cells : Should be 2.
16 bits[3:0] trigger type and level flags:
17 1 = low-to-high edge triggered.
18 2 = high-to-low edge triggered.
[all …]
H A Dgpio-zynq.txt2 -------------------------------------------
5 - #gpio-cells : Should be two
6 - First cell is the GPIO line number
7 - Second cell is used to specify optional
9 - compatible : Should be "xlnx,zynq-gpio-1.0" or
10 "xlnx,zynqmp-gpio-1.0" or "xlnx,versal-gpio-1.0
11 or "xlnx,pmc-gpio-1.0
12 - clocks : Clock specifier (see clock bindings for details)
13 - gpio-controller : Marks the device node as a GPIO controller.
14 - interrupts : Interrupt specifier (see interrupt bindings for
[all …]
H A Dgpio-omap.txt4 - compatible:
5 - "ti,omap2-gpio" for OMAP2 controllers
6 - "ti,omap3-gpio" for OMAP3 controllers
7 - "ti,omap4-gpio" for OMAP4 controllers
8 - reg : Physical base address of the controller and length of memory mapped
10 - gpio-controller : Marks the device node as a GPIO controller.
11 - #gpio-cells : Should be two.
12 - first cell is the pin number
13 - second cell is used to specify optional parameters (unused)
14 - interrupt-controller: Mark the device node as an interrupt controller.
[all …]
H A Dgpio-vf610.txt8 - compatible : Should be "fsl,<soc>-gpio", below is supported list:
9 "fsl,vf610-gpio"
10 "fsl,imx7ulp-gpio"
11 - reg : The first reg tuple represents the PORT module, the second tuple
13 - interrupts : Should be the port interrupt shared by all 32 pins.
14 - gpio-controller : Marks the device node as a gpio controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and
19 - interrupt-controller: Marks the device node as an interrupt controller.
20 - #interrupt-cells : Should be 2. The first cell is the GPIO number.
21 The second cell bits[3:0] is used to specify trigger type and level flags:
[all …]
/freebsd/sys/x86/isa/
H A Delcr.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
38 * trigger mode. All edge triggered IRQs use active-hi polarity, and
39 * all level triggered interrupts use active-lo polarity.
41 * The format of the ELCR is simple: it is a 16-bit bitmap where bit 0
43 * associated IRQ is edge triggered. If the bit is one, the IRQ is
44 * level triggered.
60 * verifying that IRQs 0, 1, 2, and 13 are all edge triggered.
90 * Returns 1 for level trigger, 0 for edge.
105 * Set the trigger mode for a specified IRQ. Mode of 0 means edge triggered,
[all …]
/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Dgpio-poweroff.txt3 The driver supports both level triggered and edge triggered power off.
9 When the power-off handler is called, the gpio is configured as an
10 output, and drive active, so triggering a level triggered power off
11 condition. This will also cause an inactive->active edge condition, so
12 triggering positive edge triggered power off. After a delay of 100ms,
13 the GPIO is set to inactive, thus causing an active->inactive edge,
14 triggering negative edge triggered power off. After another 100ms
19 - compatible : should be "gpio-poweroff".
20 - gpios : The GPIO to set high/low, see "gpios property" in
26 - input : Initially configure the GPIO line as an input. Only reconfigure
[all …]
H A Dgpio-restart.txt4 This binding supports level and edge triggered reset. At driver load
6 handler. If the optional properties 'open-source' is not found, the GPIO line
12 triggering a level triggered reset condition. This will also cause an
13 inactive->active edge condition, triggering positive edge triggered
14 reset. After a delay specified by active-delay, the GPIO is set to
15 inactive, thus causing an active->inactive edge, triggering negative edge
16 triggered reset. After a delay specified by inactive-delay, the GPIO
17 is driven active again. After a delay specified by wait-delay, the
21 - compatible : should be "gpio-restart".
22 - gpios : The GPIO to set high/low, see "gpios property" in
[all …]
H A Dgpio-restart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restar
[all...]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dimg,pdc-intc.txt10 - compatible: Specifies the compatibility list for the interrupt controller.
11 The type shall be <string> and the value shall include "img,pdc-intc".
13 - reg: Specifies the base PDC physical address(s) and size(s) of the
14 addressable register space. The type shall be <prop-encoded-array>.
16 - interrupt-controller: The presence of this property identifies the node
19 - #interrupt-cells: Specifies the number of cells needed to encode an
22 - num-perips: Number of waking peripherals.
24 - num-syswakes: Number of SysWake inputs.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
34 - <1st-cell>: The interrupt-number that identifies the interrupt source.
[all …]
H A Dopencores,or1k-pic.txt5 - compatible : should be "opencores,or1k-pic-level" for variants with
6 level triggered interrupt lines, "opencores,or1k-pic-edge" for variants with
7 edge triggered interrupt lines or "opencores,or1200-pic" for machines
8 with the non-spec compliant or1200 type implementation.
10 "opencores,or1k-pic" is also provided as an alias to "opencores,or1200-pic",
13 - interrupt-controller : Identifies the node as an interrupt controller
14 - #interrupt-cells : Specifies the number of cells needed to encode an
19 intc: interrupt-controller {
20 compatible = "opencores,or1k-pic-level";
21 interrupt-controller;
[all …]
H A Dsnps,archs-idu-intc.txt1 * ARC-HS Interrupt Distribution Unit
3 This optional 2nd level interrupt controller can be used in SMP configurations
9 - compatible: "snps,archs-idu-intc"
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
18 - bits[3:0] trigger type and level flags
19 1 = low-to-high edge triggered
20 2 = NOT SUPPORTED (high-to-low edge triggered)
21 4 = active high level-sensitive <<< DEFAULT
22 8 = NOT SUPPORTED (active low level-sensitive)
[all …]
H A Datmel,aic.txt4 - compatible: Should be:
5 - "atmel,<chip>-aic" where <chip> can be "at91rm9200", "sama5d2",
7 - "microchip,<chip>-aic" where <chip> can be "sam9x60"
9 - interrupt-controller: Identifies the node as an interrupt controller.
10 - #interrupt-cells: The number of cells to define the interrupts. It should be 3.
13 bits[3:0] trigger type and level flags:
14 1 = low-to-high edge triggered.
15 2 = high-to-low edge triggered.
16 4 = active high level-sensitive.
17 8 = active low level-sensitive.
[all …]
H A Dti,sci-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
19 triggered or level triggered interrupts and that is fixed in hardware.
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
[all …]
H A Dsifive,plic-1.0.0.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controlle
[all...]
H A Dti,sci-intr.txt6 to be driven per N output. An Interrupt Router can either handle edge triggered
7 or level triggered interrupts and that is fixed in hardware.
10 +----------------------+
12 +-------+ | +------+ +-----+ |
13 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
14 +-------+ | +------+ +-----+ | controller
15 | . . | +-------+
16 +-------+ | . . |----->| IRQ |
17 | INTA |----------->| . . | +-------+
18 +-------+ | . +-----+ |
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dsamsung-pinctrl.txt6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
[all …]
H A Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
28 [irqN]----> [gpio-bank (n)]
33 - compatible : should be "st,stih407-<pio-block>-pinctrl"
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mfd/
H A Dqcom-pm8xxx.txt1 Qualcomm PM8xxx PMIC multi-function devices
8 - compatible:
16 - #address-cells:
21 - #size-cells:
26 - interrupts:
28 Value type: <prop-encoded-array>
34 - #interrupt-cells:
39 number. The 2nd cell is the trigger type and level flags
42 1 = low-to-high edge triggered
43 2 = high-to-low edge triggered
[all …]

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