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/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright (C) 2014-2019 aQuantia Corporation
5 * Copyright (C) 2019-2020 Marvell International Ltd.
54 /* register address for bitfield tx dma good octet counter lsw [1f:0] */
56 /* register address for bitfield tx dma good packet counter lsw [1f:0] */
63 /* register address for bitfield tx dma good octet counter msw [3f:20] */
65 /* register address for bitfield tx dma good packet counter msw [3f:20] */
89 /* preprocessor definitions for msm tx unicast frames counter register */
92 /* preprocessor definitions for msm tx multicast frames counter register */
154 /* inverted bitmask for bitfield dca_en */
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-pine64-star64.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
24 phy-handle = <&phy1>;
25 phy-mode = "rgmii-id";
26 starfive,tx-use-rgmii-clk;
27 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
[all …]
H A Djh7110-starfive-visionfive-2-v1.3b.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110-starfive-visionfive-2.dtsi"
12 compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
16 starfive,tx-use-rgmii-clk;
17 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
18 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
22 starfive,tx-use-rgmii-clk;
23 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
24 assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
[all …]
H A Djh7110-milkv-mars.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
10 model = "Milk-V Mars";
15 starfive,tx-use-rgmii-clk;
16 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
17 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
29 motorcomm,tx-clk-adj-enabled;
30 motorcomm,tx-clk-10-inverted;
31 motorcomm,tx-clk-100-inverted;
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dmotorcomm,yt8xxx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Sae <frank.sae@motor-comm.com>
13 - $ref: ethernet-phy.yaml#
18 - ethernet-phy-id4f51.e91a
19 - ethernet-phy-id4f51.e91b
21 rx-internal-delay-ps:
24 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
30 tx-internal-delay-ps:
[all …]
H A Dibm,emac.txt8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
23 - mal-device : phandle of the associated McMAL node
24 - mal-tx-channel : 1 cell, index of the tx channel on McMAL associated
[all …]
/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
H A Dhw_atl2_llh_internal.h1 /* SPDX-License-Identifier: GPL-2.0-only */
36 /* inverted bitmask for bitfield rpf_new_rpf_en */
55 /* inverted bitmask for bitfield l2_uc_req_tag0{f}[2:0] */
73 /* inverted bitmask for bitfield rpf_l2_bc_req_tag */
109 /* inverted bitmask for bitfield vlan_req_tag0{f}[3:0] */
120 * Parameter: Queue {Q} | bit-level stride | range [0, 31]
135 /* tx tx_tc_q_rand_map_en bitfield definitions
144 /* inverted bitmask for bitfield tx_tc_q_rand_map_en */
153 /* tx tx_buffer_clk_gate_en bitfield definitions
162 /* inverted bitmask for bitfield tx_buffer_clk_gate_en */
[all …]
/linux/include/dt-bindings/sound/
H A Dcs35l45.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * cs35l45.h -- CS35L45 ALSA SoC audio driver DT bindings header
12 * cirrus,asp-sdout-hiz-ctrl
14 * TX_HIZ_UNUSED: TX pin high-impedance during unused slots.
15 * TX_HIZ_DISABLED: TX pin high-impedance when all channels disabled.
21 * Optional GPIOX Sub-nodes:
22 * The cs35l45 node can have up to three "cirrus,gpio-ctrlX" ('X' = [1,2,3])
23 * sub-nodes for configuring the GPIO pins.
25 * - gpio-dir : GPIO pin direction. Valid only when 'gpio-ctrl'
30 * - gpio-lvl : GPIO level. Valid only when 'gpio-ctrl' is 1 and 'gpio-dir' is 0.
[all …]
/linux/drivers/net/pcs/
H A Dpcs-xpcs-nxp.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/pcs/pcs-xpcs.h>
5 #include "pcs-xpcs.h"
67 /* In NXP SJA1105, the PCS is integrated with a PMA that has the TX lane
68 * polarity inverted by default (PLUS is MINUS, MINUS is PLUS). To obtain
69 * normal non-inverted behavior, the TX lane polarity must be inverted in the
86 /* Program TX PLL feedback divider and reference divider settings for in nxp_sja1110_pma_config()
152 /* Enable TX and RX PLLs and circuits. in nxp_sja1110_pma_config()
168 /* Program continuous-time linear equalizer (CTLE) settings. */ in nxp_sja1110_pma_config()
/linux/Documentation/devicetree/bindings/serial/
H A Dfsl-imx-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabio Estevam <festevam@gmail.com>
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
17 - items:
18 - enum:
19 - fsl,imx25-uart
[all …]
/linux/arch/powerpc/boot/dts/
H A Deiger.dts11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
40 d-cache-line-size = <32>;
[all …]
H A Darches.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
17 /dts-v1/;
20 #address-cells = <2>;
21 #size-cells = <1>;
24 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by U-Boot */
42 timebase-frequency = <0>; /* Filled in by U-Boot */
43 i-cache-line-size = <32>;
[all …]
H A Dglacier.dts4 * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
30 #address-cells = <1>;
31 #size-cells = <0>;
37 clock-frequency = <0>; /* Filled in by U-Boot */
38 timebase-frequency = <0>; /* Filled in by U-Boot */
39 i-cache-line-size = <32>;
[all …]
H A Drainier.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
H A Dsequoia.dts15 /dts-v1/;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 dcr-parent = <&{/cpus/cpu@0}>;
34 #address-cells = <1>;
35 #size-cells = <0>;
41 clock-frequency = <0>; /* Filled in by zImage */
42 timebase-frequency = <0>; /* Filled in by zImage */
43 i-cache-line-size = <32>;
44 d-cache-line-size = <32>;
[all …]
H A Dfsp2.dts12 /dts-v1/;
15 #address-cells = <2>;
16 #size-cells = <1>;
19 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by cuboot */
36 timebase-frequency = <0>; /* Filled in by cuboot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
[all …]
/linux/sound/drivers/
H A Dportman2x4.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) by Levent Guendogdu <levon@feature-it.com>
9 * - cleanup and rewrite
11 * - source code cleanup
13 * - fixed compilation problem with alsa 1.0.6a (removed MODULE_CLASSES,
17 * - added 2.6 kernel support
19 …* - added parport_unregister_driver to the startup routine if the driver fails to detect a po…
20 * - added support for all 4 output ports in portman_putmidi
22 * - added checks for opened input device in interrupt handler
24 * - ported from alsa 0.5 to 1.0
[all …]
/linux/arch/arm/boot/dts/microchip/
H A Dat91-kizbox2-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * at91-kizbox2_common.dtsi - Device Tree Include file for
6 * Copyright (C) 2014-2018 Overkiz SAS
17 stdout-path = &dbgu;
26 clock-frequency = <32768>;
30 clock-frequency = <12000000>;
34 gpio-keys {
35 compatible = "gpio-keys";
37 button-prog {
41 wakeup-source;
[all …]
H A Dsama7g5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/dma/at91.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/mfd/at91-usart.h>
19 #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-oceanic-5205-5inmfd.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "sun50i-a64-sopine.dtsi"
12 compatible = "oceanic,5205-5inmfd", "allwinner,sun50i-a64";
20 stdout-path = "serial0:115200n8";
29 pinctrl-names = "default";
30 pinctrl-0 = <&rgmii_pins>;
31 phy-mode = "rgmii";
32 phy-handle = <&ext_rgmii_phy>;
33 phy-supply = <&reg_dc1sw>;
[all …]
/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Dazoteq,iqs7211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
13 The Azoteq IQS7210A, IQS7211A and IQS7211E trackpad and touchscreen control-
14 lers employ projected-capacitance sensing and can track two contacts.
21 - azoteq,iqs7210a
22 - azoteq,iqs7211a
23 - azoteq,iqs7211e
28 irq-gpios:
[all …]
/linux/Documentation/input/devices/
H A Dwalkera0701.rst2 Walkera WK-0701 transmitter
5 Walkera WK-0701 transmitter is supplied with a ready to fly Walkera
10 http://zub.fei.tuke.sk/walkera-wk0701/
13 cg-clone http://zub.fei.tuke.sk/GIT/walkera0701-joystick
19 At back side of transmitter S-video connector can be found. Modulation
24 Cable: (walkera TX to parport)
26 Walkera WK-0701 TX S-VIDEO connector::
28 (back side of TX)
29 __ __ S-video: canon25
35 ------- 3 __________________________________|________________ 25 GND
[all …]
/linux/drivers/net/wireless/ath/
H A Dkey.c25 #define REG_READ (common->ops->read)
26 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg)
28 if (common->ops->enable_write_buffer) \
29 common->ops->enable_write_buffer((_ah));
32 if (common->ops->write_flush) \
33 common->ops->write_flush((_ah));
45 void *ah = common->ah; in ath_hw_keyreset()
47 if (entry >= common->keymax) { in ath_hw_keyreset()
73 if (common->crypt_caps & ATH_CRYPT_CAP_MIC_COMBINED) { in ath_hw_keyreset()
91 void *ah = common->ah; in ath_hw_keysetmac()
[all …]
/linux/Documentation/devicetree/bindings/input/
H A Dazoteq,iqs7222.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jeff LaBundy <jeff@labundy.com>
21 - azoteq,iqs7222a
22 - azoteq,iqs7222b
23 - azoteq,iqs7222c
24 - azoteq,iqs7222d
29 irq-gpios:
32 Specifies the GPIO connected to the device's active-low RDY output.
[all …]
/linux/Documentation/networking/device_drivers/ethernet/google/
H A Dgve.rst1 .. SPDX-License-Identifier: GPL-2.0+
12 +--------------+----------+---------+
16 +--------------+----------+---------+
18 +--------------+----------+---------+
19 |Sub-vendor ID | `0x1AE0` | Google |
20 +--------------+----------+---------+
21 |Sub-device ID | `0x0058` | |
22 +--------------+----------+---------+
24 +--------------+----------+---------+
26 +--------------+----------+---------+
[all …]

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