xref: /linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/hw_atl2_llh_internal.h (revision 4b4193256c8d3bc3a5397b5cd9494c2ad386317d)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Atlantic Network Driver
3  * Copyright (C) 2020 Marvell International Ltd.
4  */
5 
6 #ifndef HW_ATL2_LLH_INTERNAL_H
7 #define HW_ATL2_LLH_INTERNAL_H
8 
9 /* RX pif_rpf_redir_2_en_i Bitfield Definitions
10  * PORT="pif_rpf_redir_2_en_i"
11  */
12 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_ADR 0x000054C8
13 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSK 0x00001000
14 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_MSKN 0xFFFFEFFF
15 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_SHIFT 12
16 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_WIDTH 1
17 #define HW_ATL2_RPF_PIF_RPF_REDIR2_ENI_DEFAULT 0x0
18 
19 /* RX pif_rpf_rss_hash_type_i Bitfield Definitions
20  */
21 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_ADR 0x000054C8
22 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSK 0x000001FF
23 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_MSKN 0xFFFFFE00
24 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_SHIFT 0
25 #define HW_ATL2_RPF_PIF_RPF_RSS_HASH_TYPEI_WIDTH 9
26 
27 /* rx rpf_new_rpf_en bitfield definitions
28  * preprocessor definitions for the bitfield "rpf_new_rpf_en_i".
29  * port="pif_rpf_new_rpf_en_i
30  */
31 
32 /* register address for bitfield rpf_new_rpf_en */
33 #define HW_ATL2_RPF_NEW_EN_ADR 0x00005104
34 /* bitmask for bitfield rpf_new_rpf_en */
35 #define HW_ATL2_RPF_NEW_EN_MSK 0x00000800
36 /* inverted bitmask for bitfield rpf_new_rpf_en */
37 #define HW_ATL2_RPF_NEW_EN_MSKN 0xfffff7ff
38 /* lower bit position of bitfield rpf_new_rpf_en */
39 #define HW_ATL2_RPF_NEW_EN_SHIFT 11
40 /* width of bitfield rpf_new_rpf_en */
41 #define HW_ATL2_RPF_NEW_EN_WIDTH 1
42 /* default value of bitfield rpf_new_rpf_en */
43 #define HW_ATL2_RPF_NEW_EN_DEFAULT 0x0
44 
45 /* rx l2_uc_req_tag0{f}[5:0] bitfield definitions
46  * preprocessor definitions for the bitfield "l2_uc_req_tag0{f}[7:0]".
47  * parameter: filter {f} | stride size 0x8 | range [0, 37]
48  * port="pif_rpf_l2_uc_req_tag0[5:0]"
49  */
50 
51 /* register address for bitfield l2_uc_req_tag0{f}[2:0] */
52 #define HW_ATL2_RPFL2UC_TAG_ADR(filter) (0x00005114 + (filter) * 0x8)
53 /* bitmask for bitfield l2_uc_req_tag0{f}[2:0] */
54 #define HW_ATL2_RPFL2UC_TAG_MSK 0x0FC00000
55 /* inverted bitmask for bitfield l2_uc_req_tag0{f}[2:0] */
56 #define HW_ATL2_RPFL2UC_TAG_MSKN 0xF03FFFFF
57 /* lower bit position of bitfield l2_uc_req_tag0{f}[2:0] */
58 #define HW_ATL2_RPFL2UC_TAG_SHIFT 22
59 /* width of bitfield l2_uc_req_tag0{f}[2:0] */
60 #define HW_ATL2_RPFL2UC_TAG_WIDTH 6
61 /* default value of bitfield l2_uc_req_tag0{f}[2:0] */
62 #define HW_ATL2_RPFL2UC_TAG_DEFAULT 0x0
63 
64 /* rpf_l2_bc_req_tag[5:0] bitfield definitions
65  * preprocessor definitions for the bitfield "rpf_l2_bc_req_tag[5:0]".
66  * port="pifrpf_l2_bc_req_tag_i[5:0]"
67  */
68 
69 /* register address for bitfield rpf_l2_bc_req_tag */
70 #define HW_ATL2_RPF_L2_BC_TAG_ADR 0x000050F0
71 /* bitmask for bitfield rpf_l2_bc_req_tag */
72 #define HW_ATL2_RPF_L2_BC_TAG_MSK 0x0000003F
73 /* inverted bitmask for bitfield rpf_l2_bc_req_tag */
74 #define HW_ATL2_RPF_L2_BC_TAG_MSKN 0xffffffc0
75 /* lower bit position of bitfield rpf_l2_bc_req_tag */
76 #define HW_ATL2_RPF_L2_BC_TAG_SHIFT 0
77 /* width of bitfield rpf_l2_bc_req_tag */
78 #define HW_ATL2_RPF_L2_BC_TAG_WIDTH 6
79 /* default value of bitfield rpf_l2_bc_req_tag */
80 #define HW_ATL2_RPF_L2_BC_TAG_DEFAULT 0x0
81 
82 /* rx rpf_rss_red1_data_[4:0] bitfield definitions
83  * preprocessor definitions for the bitfield "rpf_rss_red1_data[4:0]".
84  * port="pif_rpf_rss_red1_data_i[4:0]"
85  */
86 
87 /* register address for bitfield rpf_rss_red1_data[4:0] */
88 #define HW_ATL2_RPF_RSS_REDIR_ADR(TC, INDEX) (0x00006200 + \
89 					(0x100 * !!((TC) > 3)) + (INDEX) * 4)
90 /* bitmask for bitfield rpf_rss_red1_data[4:0] */
91 #define HW_ATL2_RPF_RSS_REDIR_MSK(TC)  (0x00000001F << (5 * ((TC) % 4)))
92 /* lower bit position of bitfield rpf_rss_red1_data[4:0] */
93 #define HW_ATL2_RPF_RSS_REDIR_SHIFT(TC) (5 * ((TC) % 4))
94 /* width of bitfield rpf_rss_red1_data[4:0] */
95 #define HW_ATL2_RPF_RSS_REDIR_WIDTH 5
96 /* default value of bitfield rpf_rss_red1_data[4:0] */
97 #define HW_ATL2_RPF_RSS_REDIR_DEFAULT 0x0
98 
99 /* rx vlan_req_tag0{f}[3:0] bitfield definitions
100  * preprocessor definitions for the bitfield "vlan_req_tag0{f}[3:0]".
101  * parameter: filter {f} | stride size 0x4 | range [0, 15]
102  * port="pif_rpf_vlan_req_tag0[3:0]"
103  */
104 
105 /* register address for bitfield vlan_req_tag0{f}[3:0] */
106 #define HW_ATL2_RPF_VL_TAG_ADR(filter) (0x00005290 + (filter) * 0x4)
107 /* bitmask for bitfield vlan_req_tag0{f}[3:0] */
108 #define HW_ATL2_RPF_VL_TAG_MSK 0x0000F000
109 /* inverted bitmask for bitfield vlan_req_tag0{f}[3:0] */
110 #define HW_ATL2_RPF_VL_TAG_MSKN 0xFFFF0FFF
111 /* lower bit position of bitfield vlan_req_tag0{f}[3:0] */
112 #define HW_ATL2_RPF_VL_TAG_SHIFT 12
113 /* width of bitfield vlan_req_tag0{f}[3:0] */
114 #define HW_ATL2_RPF_VL_TAG_WIDTH 4
115 /* default value of bitfield vlan_req_tag0{f}[3:0] */
116 #define HW_ATL2_RPF_VL_TAG_DEFAULT 0x0
117 
118 /* RX rx_q{Q}_tc_map[2:0] Bitfield Definitions
119  * Preprocessor definitions for the bitfield "rx_q{Q}_tc_map[2:0]".
120  * Parameter: Queue {Q} | bit-level stride | range [0, 31]
121  * PORT="pif_rx_q0_tc_map_i[2:0]"
122  */
123 
124 /* Register address for bitfield rx_q{Q}_tc_map[2:0] */
125 #define HW_ATL2_RX_Q_TC_MAP_ADR(queue) \
126 	(((queue) < 32) ? 0x00005900 + ((queue) / 8) * 4 : 0)
127 /* Lower bit position of bitfield rx_q{Q}_tc_map[2:0] */
128 #define HW_ATL2_RX_Q_TC_MAP_SHIFT(queue) \
129 	(((queue) < 32) ? ((queue) * 4) % 32 : 0)
130 /* Width of bitfield rx_q{Q}_tc_map[2:0] */
131 #define HW_ATL2_RX_Q_TC_MAP_WIDTH 3
132 /* Default value of bitfield rx_q{Q}_tc_map[2:0] */
133 #define HW_ATL2_RX_Q_TC_MAP_DEFAULT 0x0
134 
135 /* tx tx_tc_q_rand_map_en bitfield definitions
136  * preprocessor definitions for the bitfield "tx_tc_q_rand_map_en".
137  * port="pif_tpb_tx_tc_q_rand_map_en_i"
138  */
139 
140 /* register address for bitfield tx_tc_q_rand_map_en */
141 #define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_ADR 0x00007900
142 /* bitmask for bitfield tx_tc_q_rand_map_en */
143 #define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSK 0x00000200
144 /* inverted bitmask for bitfield tx_tc_q_rand_map_en */
145 #define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_MSKN 0xFFFFFDFF
146 /* lower bit position of bitfield tx_tc_q_rand_map_en */
147 #define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_SHIFT 9
148 /* width of bitfield tx_tc_q_rand_map_en */
149 #define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_WIDTH 1
150 /* default value of bitfield tx_tc_q_rand_map_en */
151 #define HW_ATL2_TPB_TX_TC_Q_RAND_MAP_EN_DEFAULT 0x0
152 
153 /* tx tx_buffer_clk_gate_en bitfield definitions
154  * preprocessor definitions for the bitfield "tx_buffer_clk_gate_en".
155  * port="pif_tpb_tx_buffer_clk_gate_en_i"
156  */
157 
158 /* register address for bitfield tx_buffer_clk_gate_en */
159 #define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_ADR 0x00007900
160 /* bitmask for bitfield tx_buffer_clk_gate_en */
161 #define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSK 0x00000020
162 /* inverted bitmask for bitfield tx_buffer_clk_gate_en */
163 #define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_MSKN 0xffffffdf
164 /* lower bit position of bitfield tx_buffer_clk_gate_en */
165 #define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_SHIFT 5
166 /* width of bitfield tx_buffer_clk_gate_en */
167 #define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_WIDTH 1
168 /* default value of bitfield tx_buffer_clk_gate_en */
169 #define HW_ATL2_TPB_TX_BUF_CLK_GATE_EN_DEFAULT 0x0
170 
171 /* tx tx_q_tc_map{q} bitfield definitions
172  * preprocessor definitions for the bitfield "tx_q_tc_map{q}".
173  * parameter: queue {q} | bit-level stride | range [0, 31]
174  * port="pif_tpb_tx_q_tc_map0_i[2:0]"
175  */
176 
177 /* register address for bitfield tx_q_tc_map{q} */
178 #define HW_ATL2_TX_Q_TC_MAP_ADR(queue) \
179 	(((queue) < 32) ? 0x0000799C + ((queue) / 4) * 4 : 0)
180 /* lower bit position of bitfield tx_q_tc_map{q} */
181 #define HW_ATL2_TX_Q_TC_MAP_SHIFT(queue) \
182 	(((queue) < 32) ? ((queue) * 8) % 32 : 0)
183 /* width of bitfield tx_q_tc_map{q} */
184 #define HW_ATL2_TX_Q_TC_MAP_WIDTH 3
185 /* default value of bitfield tx_q_tc_map{q} */
186 #define HW_ATL2_TX_Q_TC_MAP_DEFAULT 0x0
187 
188 /* tx data_tc_arb_mode bitfield definitions
189  * preprocessor definitions for the bitfield "data_tc_arb_mode".
190  * port="pif_tps_data_tc_arb_mode_i"
191  */
192 
193 /* register address for bitfield data_tc_arb_mode */
194 #define HW_ATL2_TPS_DATA_TC_ARB_MODE_ADR 0x00007100
195 /* bitmask for bitfield data_tc_arb_mode */
196 #define HW_ATL2_TPS_DATA_TC_ARB_MODE_MSK 0x00000003
197 /* inverted bitmask for bitfield data_tc_arb_mode */
198 #define HW_ATL2_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffc
199 /* lower bit position of bitfield data_tc_arb_mode */
200 #define HW_ATL2_TPS_DATA_TC_ARB_MODE_SHIFT 0
201 /* width of bitfield data_tc_arb_mode */
202 #define HW_ATL2_TPS_DATA_TC_ARB_MODE_WIDTH 2
203 /* default value of bitfield data_tc_arb_mode */
204 #define HW_ATL2_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0
205 
206 /* tx data_tc{t}_credit_max[f:0] bitfield definitions
207  * preprocessor definitions for the bitfield "data_tc{t}_credit_max[f:0]".
208  * parameter: tc {t} | stride size 0x4 | range [0, 7]
209  * port="pif_tps_data_tc0_credit_max_i[15:0]"
210  */
211 
212 /* register address for bitfield data_tc{t}_credit_max[f:0] */
213 #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4)
214 /* bitmask for bitfield data_tc{t}_credit_max[f:0] */
215 #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSK 0xffff0000
216 /* inverted bitmask for bitfield data_tc{t}_credit_max[f:0] */
217 #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSKN 0x0000ffff
218 /* lower bit position of bitfield data_tc{t}_credit_max[f:0] */
219 #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_SHIFT 16
220 /* width of bitfield data_tc{t}_credit_max[f:0] */
221 #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_WIDTH 16
222 /* default value of bitfield data_tc{t}_credit_max[f:0] */
223 #define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0
224 
225 /* tx data_tc{t}_weight[e:0] bitfield definitions
226  * preprocessor definitions for the bitfield "data_tc{t}_weight[e:0]".
227  * parameter: tc {t} | stride size 0x4 | range [0, 7]
228  * port="pif_tps_data_tc0_weight_i[14:0]"
229  */
230 
231 /* register address for bitfield data_tc{t}_weight[e:0] */
232 #define HW_ATL2_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4)
233 /* bitmask for bitfield data_tc{t}_weight[e:0] */
234 #define HW_ATL2_TPS_DATA_TCTWEIGHT_MSK 0x00007fff
235 /* inverted bitmask for bitfield data_tc{t}_weight[e:0] */
236 #define HW_ATL2_TPS_DATA_TCTWEIGHT_MSKN 0xffff8000
237 /* lower bit position of bitfield data_tc{t}_weight[e:0] */
238 #define HW_ATL2_TPS_DATA_TCTWEIGHT_SHIFT 0
239 /* width of bitfield data_tc{t}_weight[e:0] */
240 #define HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH 15
241 /* default value of bitfield data_tc{t}_weight[e:0] */
242 #define HW_ATL2_TPS_DATA_TCTWEIGHT_DEFAULT 0x0
243 
244 /* tx interrupt moderation control register definitions
245  * Preprocessor definitions for TX Interrupt Moderation Control Register
246  * Base Address: 0x00007c28
247  * Parameter: queue {Q} | stride size 0x4 | range [0, 31]
248  */
249 
250 #define HW_ATL2_TX_INTR_MODERATION_CTL_ADR(queue) (0x00007c28u + (queue) * 0x40)
251 
252 /* Launch time control register */
253 #define HW_ATL2_LT_CTRL_ADR 0x00007a1c
254 
255 #define HW_ATL2_LT_CTRL_AVB_LEN_CMP_TRSHLD_MSK 0xFFFF0000
256 #define HW_ATL2_LT_CTRL_AVB_LEN_CMP_TRSHLD_SHIFT 16
257 
258 #define HW_ATL2_LT_CTRL_CLK_RATIO_MSK 0x0000FF00
259 #define HW_ATL2_LT_CTRL_CLK_RATIO_SHIFT 8
260 #define HW_ATL2_LT_CTRL_CLK_RATIO_QUATER_SPEED 4
261 #define HW_ATL2_LT_CTRL_CLK_RATIO_HALF_SPEED 2
262 #define HW_ATL2_LT_CTRL_CLK_RATIO_FULL_SPEED 1
263 
264 #define HW_ATL2_LT_CTRL_25G_MODE_SUPPORT_MSK 0x00000008
265 #define HW_ATL2_LT_CTRL_25G_MODE_SUPPORT_SHIFT 3
266 
267 #define HW_ATL2_LT_CTRL_LINK_SPEED_MSK 0x00000007
268 #define HW_ATL2_LT_CTRL_LINK_SPEED_SHIFT 0
269 
270 /* FPGA VER register */
271 #define HW_ATL2_FPGA_VER_ADR 0x000000f4
272 #define HW_ATL2_FPGA_VER_U32(mj, mi, bl, rv) \
273 	((((mj) & 0xff) << 24) | \
274 	 (((mi) & 0xff) << 16) | \
275 	 (((bl) & 0xff) << 8) | \
276 	 (((rv) & 0xff) << 0))
277 
278 /* ahb_mem_addr{f}[31:0] Bitfield Definitions
279  * Preprocessor definitions for the bitfield "ahb_mem_addr{f}[31:0]".
280  * Parameter: filter {f} | stride size 0x10 | range [0, 127]
281  * PORT="ahb_mem_addr{f}[31:0]"
282  */
283 
284 /* Register address for bitfield ahb_mem_addr{f}[31:0] */
285 #define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_ADR(filter) \
286 	(0x00014000u + (filter) * 0x10)
287 /* Bitmask for bitfield ahb_mem_addr{f}[31:0] */
288 #define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_MSK 0xFFFFFFFFu
289 /* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */
290 #define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_MSKN 0x00000000u
291 /* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */
292 #define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_SHIFT 0
293 /* Width of bitfield ahb_mem_addr{f}[31:0] */
294 #define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_WIDTH 31
295 /* Default value of bitfield ahb_mem_addr{f}[31:0] */
296 #define HW_ATL2_RPF_ACT_RSLVR_REQ_TAG_DEFAULT 0x0
297 
298 /* Register address for bitfield ahb_mem_addr{f}[31:0] */
299 #define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_ADR(filter) \
300 	(0x00014004u + (filter) * 0x10)
301 /* Bitmask for bitfield ahb_mem_addr{f}[31:0] */
302 #define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_MSK 0xFFFFFFFFu
303 /* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */
304 #define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_MSKN 0x00000000u
305 /* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */
306 #define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_SHIFT 0
307 /* Width of bitfield ahb_mem_addr{f}[31:0] */
308 #define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_WIDTH 31
309 /* Default value of bitfield ahb_mem_addr{f}[31:0] */
310 #define HW_ATL2_RPF_ACT_RSLVR_TAG_MASK_DEFAULT 0x0
311 
312 /* Register address for bitfield ahb_mem_addr{f}[31:0] */
313 #define HW_ATL2_RPF_ACT_RSLVR_ACTN_ADR(filter) \
314 	(0x00014008u + (filter) * 0x10)
315 /* Bitmask for bitfield ahb_mem_addr{f}[31:0] */
316 #define HW_ATL2_RPF_ACT_RSLVR_ACTN_MSK 0x000007FFu
317 /* Inverted bitmask for bitfield ahb_mem_addr{f}[31:0] */
318 #define HW_ATL2_RPF_ACT_RSLVR_ACTN_MSKN 0xFFFFF800u
319 /* Lower bit position of bitfield ahb_mem_addr{f}[31:0] */
320 #define HW_ATL2_RPF_ACT_RSLVR_ACTN_SHIFT 0
321 /* Width of bitfield ahb_mem_addr{f}[31:0] */
322 #define HW_ATL2_RPF_ACT_RSLVR_ACTN_WIDTH 10
323 /* Default value of bitfield ahb_mem_addr{f}[31:0] */
324 #define HW_ATL2_RPF_ACT_RSLVR_ACTN_DEFAULT 0x0
325 
326 /* rpf_rec_tab_en[15:0] Bitfield Definitions
327  * Preprocessor definitions for the bitfield "rpf_rec_tab_en[15:0]".
328  * PORT="pif_rpf_rec_tab_en[15:0]"
329  */
330 /* Register address for bitfield rpf_rec_tab_en[15:0] */
331 #define HW_ATL2_RPF_REC_TAB_EN_ADR 0x00006ff0u
332 /* Bitmask for bitfield rpf_rec_tab_en[15:0] */
333 #define HW_ATL2_RPF_REC_TAB_EN_MSK 0x0000FFFFu
334 /* Inverted bitmask for bitfield rpf_rec_tab_en[15:0] */
335 #define HW_ATL2_RPF_REC_TAB_EN_MSKN 0xFFFF0000u
336 /* Lower bit position of bitfield rpf_rec_tab_en[15:0] */
337 #define HW_ATL2_RPF_REC_TAB_EN_SHIFT 0
338 /* Width of bitfield rpf_rec_tab_en[15:0] */
339 #define HW_ATL2_RPF_REC_TAB_EN_WIDTH 16
340 /* Default value of bitfield rpf_rec_tab_en[15:0] */
341 #define HW_ATL2_RPF_REC_TAB_EN_DEFAULT 0x0
342 
343 /* Register address for firmware shared input buffer */
344 #define HW_ATL2_MIF_SHARED_BUFFER_IN_ADR(dword) (0x00012000U + (dword) * 0x4U)
345 /* Register address for firmware shared output buffer */
346 #define HW_ATL2_MIF_SHARED_BUFFER_OUT_ADR(dword) (0x00013000U + (dword) * 0x4U)
347 
348 /* pif_host_finished_buf_wr_i Bitfield Definitions
349  * Preprocessor definitions for the bitfield "pif_host_finished_buf_wr_i".
350  * PORT="pif_host_finished_buf_wr_i"
351  */
352 /* Register address for bitfield rpif_host_finished_buf_wr_i */
353 #define HW_ATL2_MIF_HOST_FINISHED_WRITE_ADR 0x00000e00u
354 /* Bitmask for bitfield pif_host_finished_buf_wr_i */
355 #define HW_ATL2_MIF_HOST_FINISHED_WRITE_MSK 0x00000001u
356 /* Inverted bitmask for bitfield pif_host_finished_buf_wr_i */
357 #define HW_ATL2_MIF_HOST_FINISHED_WRITE_MSKN 0xFFFFFFFEu
358 /* Lower bit position of bitfield pif_host_finished_buf_wr_i */
359 #define HW_ATL2_MIF_HOST_FINISHED_WRITE_SHIFT 0
360 /* Width of bitfield pif_host_finished_buf_wr_i */
361 #define HW_ATL2_MIF_HOST_FINISHED_WRITE_WIDTH 1
362 /* Default value of bitfield pif_host_finished_buf_wr_i */
363 #define HW_ATL2_MIF_HOST_FINISHED_WRITE_DEFAULT 0x0
364 
365 /* pif_mcp_finished_buf_rd_i Bitfield Definitions
366  * Preprocessor definitions for the bitfield "pif_mcp_finished_buf_rd_i".
367  * PORT="pif_mcp_finished_buf_rd_i"
368  */
369 /* Register address for bitfield pif_mcp_finished_buf_rd_i */
370 #define HW_ATL2_MIF_MCP_FINISHED_READ_ADR 0x00000e04u
371 /* Bitmask for bitfield pif_mcp_finished_buf_rd_i */
372 #define HW_ATL2_MIF_MCP_FINISHED_READ_MSK 0x00000001u
373 /* Inverted bitmask for bitfield pif_mcp_finished_buf_rd_i */
374 #define HW_ATL2_MIF_MCP_FINISHED_READ_MSKN 0xFFFFFFFEu
375 /* Lower bit position of bitfield pif_mcp_finished_buf_rd_i */
376 #define HW_ATL2_MIF_MCP_FINISHED_READ_SHIFT 0
377 /* Width of bitfield pif_mcp_finished_buf_rd_i */
378 #define HW_ATL2_MIF_MCP_FINISHED_READ_WIDTH 1
379 /* Default value of bitfield pif_mcp_finished_buf_rd_i */
380 #define HW_ATL2_MIF_MCP_FINISHED_READ_DEFAULT 0x0
381 
382 /* Register address for bitfield pif_mcp_boot_reg */
383 #define HW_ATL2_MIF_BOOT_REG_ADR 0x00003040u
384 
385 #define HW_ATL2_MCP_HOST_REQ_INT_READY BIT(0)
386 
387 #define HW_ATL2_MCP_HOST_REQ_INT_ADR 0x00000F00u
388 #define HW_ATL2_MCP_HOST_REQ_INT_SET_ADR 0x00000F04u
389 #define HW_ATL2_MCP_HOST_REQ_INT_CLR_ADR 0x00000F08u
390 
391 #endif /* HW_ATL2_LLH_INTERNAL_H */
392