Home
last modified time | relevance | path

Searched +full:i +full:- +full:tlb +full:- +full:size (Results 1 – 25 of 395) sorted by relevance

12345678910>>...16

/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
[all …]
H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
[all …]
/linux/arch/sparc/mm/
H A Dhugetlbpage.c1 // SPDX-License-Identifier: GPL-2.0
3 * SPARC64 Huge TLB page support.
17 #include <asm/tlb.h>
159 unsigned long size = 1UL << huge_tte_to_shift(pte); in huge_tte_to_size() local
161 if (size == REAL_HPAGE_SIZE) in huge_tte_to_size()
162 size = HPAGE_SIZE; in huge_tte_to_size()
163 return size; in huge_tte_to_size()
224 unsigned long i, size; in __set_huge_pte_at() local
227 size = huge_tte_to_size(entry); in __set_huge_pte_at()
230 if (size >= PUD_SIZE) in __set_huge_pte_at()
[all …]
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
[all …]
/linux/sound/pci/trident/
H A Dtrident_memory.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Trident 4DWave-NX memory page allocation (TLB area)
23 (trident)->tlb.entries[page] = cpu_to_le32((addr) & ~(SNDRV_TRIDENT_PAGE_SIZE-1))
25 (dma_addr_t)le32_to_cpu((trident->tlb.entries[page]) & ~(SNDRV_TRIDENT_PAGE_SIZE - 1))
28 /* page size == SNDRV_TRIDENT_PAGE_SIZE */
29 #define ALIGN_PAGE_SIZE PAGE_SIZE /* minimum page size for allocation */
31 /* fill TLB entrie(s) corresponding to page with ptr */
33 /* fill TLB entrie(s) corresponding to page with silence pointer */
34 #define set_silent_tlb(trident,page) __set_tlb_bus(trident, page, trident->tlb.silent_page->addr)
43 /* page size == SNDRV_TRIDENT_PAGE_SIZE x 2*/
[all …]
/linux/kernel/dma/
H A Dswiotlb.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * I/O TLBs (aka DMA address translation hardware).
9 * Copyright (C) 2000, 2003 Hewlett-Packard Co
10 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * 03/05/07 davidm Switch from PCI-DMA to generic device DMA API.
14 * unnecessary i-cache flushing.
21 #define pr_fmt(fmt) "software IO TLB: " fmt
27 #include <linux/dma-direct.h>
28 #include <linux/dma-map-ops.h>
33 #include <linux/iommu-helper.h>
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmicrowatt.dts1 /dts-v1/;
4 #size-cells = <0x02>;
5 #address-cells = <0x02>;
6 model-name = "microwatt";
7 compatible = "microwatt-soc";
13 reserved-memory {
14 #size-cells = <0x02>;
15 #address-cells = <0x02>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
[all …]
/linux/include/asm-generic/
H A Dtlb.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidation
218 tlb_remove_table(tlb,page) global() argument
279 tlb_delay_rmap(tlb) global() argument
293 tlb_delay_rmap(tlb) global() argument
294 tlb_flush_rmaps(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_flush_rmaps() argument
362 __tlb_adjust_range(struct mmu_gather * tlb,unsigned long address,unsigned int range_size) __tlb_adjust_range() argument
370 __tlb_reset_range(struct mmu_gather * tlb) __tlb_reset_range() argument
404 tlb_flush(struct mmu_gather * tlb) tlb_flush() argument
418 tlb_flush(struct mmu_gather * tlb) tlb_flush() argument
437 tlb_update_vma_flags(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_update_vma_flags() argument
455 tlb_flush_mmu_tlbonly(struct mmu_gather * tlb) tlb_flush_mmu_tlbonly() argument
469 tlb_remove_page_size(struct mmu_gather * tlb,struct page * page,int page_size) tlb_remove_page_size() argument
476 __tlb_remove_page(struct mmu_gather * tlb,struct page * page,bool delay_rmap) __tlb_remove_page() argument
486 tlb_remove_page(struct mmu_gather * tlb,struct page * page) tlb_remove_page() argument
491 tlb_remove_ptdesc(struct mmu_gather * tlb,void * pt) tlb_remove_ptdesc() argument
497 tlb_remove_page_ptdesc(struct mmu_gather * tlb,struct ptdesc * pt) tlb_remove_page_ptdesc() argument
502 tlb_change_page_size(struct mmu_gather * tlb,unsigned int page_size) tlb_change_page_size() argument
515 tlb_get_unmap_shift(struct mmu_gather * tlb) tlb_get_unmap_shift() argument
529 tlb_get_unmap_size(struct mmu_gather * tlb) tlb_get_unmap_size() argument
539 tlb_start_vma(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_start_vma() argument
550 tlb_end_vma(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_end_vma() argument
574 tlb_flush_pte_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pte_range() argument
575 tlb_flush_pte_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pte_range() argument
581 tlb_flush_pmd_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pmd_range() argument
582 tlb_flush_pmd_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pmd_range() argument
588 tlb_flush_pud_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pud_range() argument
589 tlb_flush_pud_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_pud_range() argument
595 tlb_flush_p4d_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_p4d_range() argument
596 tlb_flush_p4d_range(struct mmu_gather * tlb,unsigned long address,unsigned long size) tlb_flush_p4d_range() argument
603 __tlb_remove_tlb_entry(struct mmu_gather * tlb,pte_t * ptep,unsigned long address) __tlb_remove_tlb_entry() argument
615 tlb_remove_tlb_entry(tlb,ptep,address) global() argument
628 tlb_remove_tlb_entries(struct mmu_gather * tlb,pte_t * ptep,unsigned int nr,unsigned long address) tlb_remove_tlb_entries() argument
641 tlb_remove_huge_tlb_entry(h,tlb,ptep,address) global() argument
660 __tlb_remove_pmd_tlb_entry(tlb,pmdp,address) global() argument
663 tlb_remove_pmd_tlb_entry(tlb,pmdp,address) global() argument
674 __tlb_remove_pud_tlb_entry(tlb,pudp,address) global() argument
677 tlb_remove_pud_tlb_entry(tlb,pudp,address) global() argument
702 pte_free_tlb(tlb,ptep,address) global() argument
711 pmd_free_tlb(tlb,pmdp,address) global() argument
720 pud_free_tlb(tlb,pudp,address) global() argument
729 p4d_free_tlb(tlb,pudp,address) global() argument
[all...]
/linux/mm/
H A Dmmu_gather.c14 #include <asm/tlb.h>
18 static bool tlb_next_batch(struct mmu_gather *tlb) in tlb_next_batch() argument
23 if (tlb->delayed_rmap && tlb->active != &tlb->local) in tlb_next_batch()
26 batch = tlb->activ in tlb_next_batch()
55 for (int i = 0; i < batch->nr; i++) { tlb_flush_rmap_batch() local
82 tlb_flush_rmaps(struct mmu_gather * tlb,struct vm_area_struct * vma) tlb_flush_rmaps() argument
144 tlb_batch_pages_flush(struct mmu_gather * tlb) tlb_batch_pages_flush() argument
153 tlb_batch_list_free(struct mmu_gather * tlb) tlb_batch_list_free() argument
164 __tlb_remove_folio_pages_size(struct mmu_gather * tlb,struct page * page,unsigned int nr_pages,bool delay_rmap,int page_size) __tlb_remove_folio_pages_size() argument
205 __tlb_remove_folio_pages(struct mmu_gather * tlb,struct page * page,unsigned int nr_pages,bool delay_rmap) __tlb_remove_folio_pages() argument
212 __tlb_remove_page_size(struct mmu_gather * tlb,struct page * page,bool delay_rmap,int page_size) __tlb_remove_page_size() argument
224 int i; __tlb_remove_table_free() local
302 tlb_table_invalidate(struct mmu_gather * tlb) tlb_table_invalidate() argument
320 tlb_table_flush(struct mmu_gather * tlb) tlb_table_flush() argument
331 tlb_remove_table(struct mmu_gather * tlb,void * table) tlb_remove_table() argument
350 tlb_table_init(struct mmu_gather * tlb) tlb_table_init() argument
357 tlb_table_flush(struct mmu_gather * tlb) tlb_table_flush() argument
358 tlb_table_init(struct mmu_gather * tlb) tlb_table_init() argument
362 tlb_flush_mmu_free(struct mmu_gather * tlb) tlb_flush_mmu_free() argument
370 tlb_flush_mmu(struct mmu_gather * tlb) tlb_flush_mmu() argument
376 __tlb_gather_mmu(struct mmu_gather * tlb,struct mm_struct * mm,bool fullmm) __tlb_gather_mmu() argument
409 tlb_gather_mmu(struct mmu_gather * tlb,struct mm_struct * mm) tlb_gather_mmu() argument
425 tlb_gather_mmu_fullmm(struct mmu_gather * tlb,struct mm_struct * mm) tlb_gather_mmu_fullmm() argument
437 tlb_finish_mmu(struct mmu_gather * tlb) tlb_finish_mmu() argument
[all...]
/linux/arch/powerpc/mm/book3s64/
H A Dhash_tlb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * TLB and MMU hash table.
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
25 #include <asm/tlb.h>
27 #include <asm/pte-walk.h>
49 int i, offset; in hpte_need_flush() local
51 i = batch->index; in hpte_need_flush()
54 * Get page size (maybe move back to caller). in hpte_need_flush()
57 * for SPEs, we obtain the page size from the slice, which thus in hpte_need_flush()
64 /* Mask the address for the correct page size */ in hpte_need_flush()
[all …]
H A Dhash_native.c1 // SPDX-License-Identifier: GPL-2.0-or-later
23 #include <asm/tlb.h>
27 #include <asm/ppc-opcode.h>
28 #include <asm/feature-fixups.h>
30 #include <misc/cxl-base.h>
95 va &= ~((1ul << (64 - 52)) - 1); in ___tlbie()
100 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) in ___tlbie()
104 /* We need 14 to 14 + i bits of va */ in ___tlbie()
106 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1); in ___tlbie()
119 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206) in ___tlbie()
[all …]
H A Dradix_tlb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TLB flush routines for radix kernels.
5 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
15 #include <asm/ppc-opcode.h>
16 #include <asm/tlb.h>
26 * i.e., r=1 and is=01 or is=10 or is=11
39 : : "r"(rb), "r"(rs), "i"(ric), "i"(prs) in tlbiel_radix_set_isa300()
50 * Flush the first set of the TLB, and the entire Page Walk Cache in tlbiel_all_isa300()
52 * TLB. in tlbiel_all_isa300()
95 WARN(1, "%s called on pre-POWER9 CPU\n", __func__); in radix__tlbiel_all()
[all …]
/linux/Documentation/core-api/
H A Dcachetlb.rst2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
[all …]
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
[all …]
/linux/arch/nios2/kernel/
H A Dcpuinfo.c1 // SPDX-License-Identifier: GPL-2.0-or-later
41 if (!of_property_read_bool(cpu, "altr,has-initda")) in setup_cpuinfo()
43 "hardware system to have more than 4-byte line data " in setup_cpuinfo()
46 cpuinfo.cpu_clock_freq = fcpu(cpu, "clock-frequency"); in setup_cpuinfo()
54 cpuinfo.has_div = of_property_read_bool(cpu, "altr,has-div"); in setup_cpuinfo()
55 cpuinfo.has_mul = of_property_read_bool(cpu, "altr,has-mul"); in setup_cpuinfo()
56 cpuinfo.has_mulx = of_property_read_bool(cpu, "altr,has-mulx"); in setup_cpuinfo()
57 cpuinfo.has_bmx = of_property_read_bool(cpu, "altr,has-bmx"); in setup_cpuinfo()
58 cpuinfo.has_cdx = of_property_read_bool(cpu, "altr,has-cdx"); in setup_cpuinfo()
59 cpuinfo.mmu = of_property_read_bool(cpu, "altr,has-mmu"); in setup_cpuinfo()
[all …]
/linux/arch/parisc/kernel/
H A Dcache.c6 * Copyright (C) 1999-2006 Helge Deller <deller@gmx.de> (07-13-1999)
10 * Cache and TLB management
55 void flush_data_cache_local(void *); /* flushes local data-cache only */
56 void flush_instruction_cache_local(void); /* flushes local code-cache only */
60 /* On some machines (i.e., ones with the Merced bus), there can be
62 * by software. We need a spinlock around all TLB flushes to ensure
125 test_bit(PG_dcache_dirty, &folio->flags)) { in __update_cache()
126 while (nr--) in __update_cache()
128 clear_bit(PG_dcache_dirty, &folio->flags); in __update_cache()
130 while (nr--) in __update_cache()
[all …]
/linux/arch/microblaze/include/asm/
H A Dmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
27 unsigned long w:1; /* Write-thru cache mode */
28 unsigned long i:1; /* Cache inhibited */ member
43 unsigned long t:1; /* Normal or I/O type */
46 unsigned long n:1; /* No-execute */
51 extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
52 extern void _tlbia(void); /* invalidate all TLB entries */
55 * tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB
[all …]
/linux/arch/parisc/include/uapi/asm/
H A Dpdc.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/
15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */
16 #define PDC_ERROR -3 /* Call could not complete without an error */
17 #define PDC_NE_MOD -5 /* Module not found */
18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */
19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */
20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */
21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */
22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */
[all …]
/linux/arch/powerpc/include/asm/nohash/32/
H A Dpte-44x.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 * Because of the 3 word TLB entries to support 36-bit addressing,
11 * are easily loaded during exception processing. I decided to
14 * in as sensibly as they can be in the area below a 4KB page size
16 * ERPN fields in the TLB. -Matt
19 * easier to move into the TLB from the PTE. -BenH.
21 * Note that these bits preclude future use of a page size
25 * PPC 440 core has following TLB attribute fields;
29 * RPN................................. - - - - - - ERPN.......
33 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
[all …]
/linux/arch/alpha/kernel/
H A Dpci_iommu.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/dma-map-ops.h>
15 #include <linux/iommu-helper.h>
44 return (paddr >> (PAGE_SHIFT-1)) | 1; in mk_iommu_pte()
68 /* Note that the TLB lookup logic uses bitwise concatenation, in iommu_arena_new_node()
70 the size of the window. Retain the align parameter so that in iommu_arena_new_node()
71 particular systems can over-align the arena. */ in iommu_arena_new_node()
76 arena->ptes = memblock_alloc_or_panic(mem_size, align); in iommu_arena_new_node()
78 spin_lock_init(&arena->lock); in iommu_arena_new_node()
79 arena->hose = hose; in iommu_arena_new_node()
[all …]
/linux/drivers/gpu/drm/msm/
H A Dmsm_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
8 #include <linux/io-pgtable.h>
24 const struct iommu_flush_ops *tlb; member
38 size_t size, size_t *count) in calc_pgsize() argument
45 /* Page sizes supported by the hardware and small enough for @size */ in calc_pgsize()
46 pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0); in calc_pgsize()
52 /* Make sure we have at least one suitable page size */ in calc_pgsize()
55 /* Pick the biggest page size remaining */ in calc_pgsize()
61 /* Find the next biggest support page size, if it exists */ in calc_pgsize()
[all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dpipeline.json10 "BriefDescription": "Number of I-ERAT reloads"
25 …"BriefDescription": "Finish stall because the NTF instruction was a multi-cycle instruction issued…
35 …"BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a differ…
40 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without confl…
80 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
95 …"BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from anothe…
110 "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K"
115 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispa…
120 …"BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G (hpt mode) and 1G (radi…
160 …"BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data fro…
[all …]
/linux/arch/sparc/kernel/
H A Dtsb.S1 /* SPDX-License-Identifier: GPL-2.0 */
17 /* Invoked from TLB miss handler, we are in the
23 * %g3: FAULT_CODE_{D,I}TLB
46 * %g1 -- PAGE_SIZE TSB entry address
47 * %g3 -- FAULT_CODE_{D,I}TLB
48 * %g4 -- missing virtual address
49 * %g6 -- TAG TARGET (vaddr >> 22)
67 cmp %g5, -1
106 * %g1 -- TSB entry address
107 * %g3 -- FAULT_CODE_{D,I}TLB
[all …]
/linux/arch/arc/mm/
H A Dtlbex.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TLB Exception Handling for ARC
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -MMU v1: moved out legacy code into a separate file
9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * -For MMU V2, we need not do heuristics at the time of committing a D-TLB
14 * entry, so that it doesn't knock out its I-TLB entry
15 * -Some more fine tuning:
19 * -Practically rewrote the I/D TLB Miss handlers
26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
[all …]
/linux/arch/x86/mm/
H A Dpgtable.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <asm/tlb.h>
11 phys_addr_t physical_mask __ro_after_init = (1ULL << __PHYSICAL_MASK_SHIFT) - 1;
24 void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) in paravirt_tlb_remove_table()
29 tlb_remove_page(tlb, ptdesc_page(ptdesc));
33 void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table) in pte_alloc_one()
35 tlb_remove_table(tlb, table);
50 return -EINVA in setup_userpte()
23 paravirt_tlb_remove_table(struct mmu_gather * tlb,void * table) paravirt_tlb_remove_table() argument
53 ___pte_free_tlb(struct mmu_gather * tlb,struct page * pte) ___pte_free_tlb() argument
61 ___pmd_free_tlb(struct mmu_gather * tlb,pmd_t * pmd) ___pmd_free_tlb() argument
77 ___pud_free_tlb(struct mmu_gather * tlb,pud_t * pud) ___pud_free_tlb() argument
87 ___p4d_free_tlb(struct mmu_gather * tlb,p4d_t * p4d) ___p4d_free_tlb() argument
218 int i; free_pmds() local
233 int i; preallocate_pmds() local
291 int i; pgd_mop_up_pmds() local
312 int i; pgd_prepopulate_pmd() local
336 int i; pgd_prepopulate_user_pmd() local
832 int i; pud_free_pmd_page() local
[all...]

12345678910>>...16