Lines Matching +full:i +full:- +full:tlb +full:- +full:size
1 /* SPDX-License-Identifier: GPL-2.0 */
17 /* Invoked from TLB miss handler, we are in the
23 * %g3: FAULT_CODE_{D,I}TLB
46 * %g1 -- PAGE_SIZE TSB entry address
47 * %g3 -- FAULT_CODE_{D,I}TLB
48 * %g4 -- missing virtual address
49 * %g6 -- TAG TARGET (vaddr >> 22)
67 cmp %g5, -1
106 * %g1 -- TSB entry address
107 * %g3 -- FAULT_CODE_{D,I}TLB
108 * %g4 -- missing virtual address
109 * %g6 -- TAG TARGET (vaddr >> 22)
110 * %g7 -- page table physical address
131 * to do so, then return from the trap to replay the TLB
135 * pages where we don't really have a non-atomic context
143 cmp %g1, -1
170 * %g1 -- TSB entry address
171 * %g3 -- FAULT_CODE_{D,I}TLB
172 * %g5 -- valid PTE
173 * %g6 -- TAG TARGET (vaddr >> 22)
179 /* Finally, load TLB and return from trap. */
197 * to the sun4v tlb load code. The registers are setup
204 * The sun4v TLB load wants the PTE in %g3 so we fix that
233 * to the sun4v tlb load code. The registers are setup
240 * The sun4v TLB load wants the PTE in %g3 so we fix that
327 .size __tsb_insert, .-__tsb_insert
355 .size tsb_flush, .-tsb_flush
364 * %o4: Secondary context to load, if non-zero
394 mov -1, %g3
413 cmp %g3, -1
461 .size __tsb_context_switch, .-__tsb_context_switch
487 90: andcc %o0, (64 - 1), %g0
500 sllx %g2, 22, %o4 /* TAG --> VADDR */
508 and %o4, %o3, %o4 /* Mask with new_tsb_nents-1 */
521 .size copy_tsb, .-copy_tsb
527 tsb_init: /* %o0 = TSB vaddr, %o1 = size in bytes */
560 .size tsb_init, .-tsb_init
591 .size NGtsb_init, .-NGtsb_init