22 #include <asm/cpu-type.h>
26 #include <asm/tlb.h>
32  * LOONGSON-2 has a 4 entry itlb which is a subset of jtlb, LOONGSON-3 has
52 	if (vma->vm_flags & VM_EXEC)  in flush_micro_tlb_vm()
111 	struct mm_struct *mm = vma->vm_mm;  in local_flush_tlb_range()
115 		unsigned long size, flags;  in local_flush_tlb_range()  local
120 		size = (end - start) >> (PAGE_SHIFT + 1);  in local_flush_tlb_range()
121 		if (size <= (current_cpu_data.tlbsizeftlbsets ?  in local_flush_tlb_range()
170 	unsigned long size, flags;  in local_flush_tlb_kernel_range()  local
173 	size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;  in local_flush_tlb_kernel_range()
174 	size = (size + 1) >> 1;  in local_flush_tlb_kernel_range()
175 	if (size <= (current_cpu_data.tlbsizeftlbsets ?  in local_flush_tlb_kernel_range()
181 		end += ((PAGE_SIZE << 1) - 1);  in local_flush_tlb_kernel_range()
217 	if (cpu_context(cpu, vma->vm_mm) != 0) {  in local_flush_tlb_page()
229 			write_c0_memorymapid(cpu_asid(cpu, vma->vm_mm));  in local_flush_tlb_page()
231 			write_c0_entryhi(page | cpu_asid(cpu, vma->vm_mm));  in local_flush_tlb_page()
292  * updates the TLB with the new pte(s), and another which also checks
308 	if (current->active_mm != vma->vm_mm)  in __update_tlb()
321 	pgdp = pgd_offset(vma->vm_mm, address);  in __update_tlb()
358 		write_c0_entrylo0(pte_to_entrylo(ptep->pte_high));  in __update_tlb()
360 			writex_c0_entrylo0(ptep->pte_low & _PFNX_MASK);  in __update_tlb()
362 		write_c0_entrylo1(pte_to_entrylo(ptep->pte_high));  in __update_tlb()
364 			writex_c0_entrylo1(ptep->pte_low & _PFNX_MASK);  in __update_tlb()
366 		write_c0_entrylo0(ptep->pte_high);  in __update_tlb()
368 		write_c0_entrylo1(ptep->pte_high);  in __update_tlb()
437 	static unsigned int mask = -1;  in has_transparent_hugepage()
439 	if (mask == -1) {	/* first call comes during __init */  in has_transparent_hugepage()
456  * Used for loading TLB entries before trap_init() has started, when we
479 	if (--temp_tlb_entry < wired) {  in add_temporary_entry()
481 		       "No TLB space left for add_temporary_entry\n");  in add_temporary_entry()
482 		ret = -ENOSPC;  in add_temporary_entry()
517 	long v = *(unsigned long *)a - *(unsigned long *)b;  in r4k_vpn_cmp()
518 	int s = sizeof(long) > sizeof(int) ? sizeof(long) * 8 - 1: 0;  in r4k_vpn_cmp()
523  * Initialise all TLB entries with unique values that do not clash with
534 	int cnt, ent, idx, i;  in r4k_tlb_uniquify()  local
536 	vpn_mask = GENMASK(cpu_vmbits - 1, 13);  in r4k_tlb_uniquify()
548 	for (i = start, cnt = 0; i < tlbsize; i++, cnt++) {  in r4k_tlb_uniquify()
551 		write_c0_index(i);  in r4k_tlb_uniquify()
574 	for (i = start; i < tlbsize; i++)  in r4k_tlb_uniquify()
583 				write_c0_index(i);  in r4k_tlb_uniquify()
605  * Configure TLB (for init or after a CPU has been powered off).
611 	 *   - On R4600 1.7 the tlbp never hits for pages smaller than  in r4k_tlb_configure()
613 	 *   - The entire mm handling assumes the c0_pagemask register to  in r4k_tlb_configure()
614 	 *     be set to fixed-size pages.  in r4k_tlb_configure()
640 	temp_tlb_entry = current_cpu_data.tlbsize - 1;  in r4k_tlb_configure()
646 	/* Did I tell you that ARC SUCKS?  */  in r4k_tlb_configure()
655 			int wired = current_cpu_data.tlbsize - ntlb;  in tlb_init()
657 			write_c0_index(wired-1);  in tlb_init()
658 			printk("Restricting TLB to %d entries\n", ntlb);  in tlb_init()